The future of mixed-signal, memory, and microprocessor technologies are dependent on ever increasing analog and
digital integration and higher cell densities. However, device variability creates challenges at each new technology node
which decreases yield, performance, and noise margins. At these device dimensions the low-frequency noise is
dominated by the influence of one or more traps capturing and emitting charge in the oxide creating wide variations in
noise from otherwise identical devices. Existing processes of record have been extended well beyond the ranges
previously deemed feasible or reliable and single electron events and random telegraph noise signals become important.
The high speed low capacitance probe presented here is a flexible / tailorable tool for internal node testing on Radio
Frequency Integrated Circuits (RFIC). The probe utilizes the mutual capacitive coupling between two wires. In this
case, a tungsten whisker and the inner conductor of a coaxial cable forms a capacitor, enabling extremely low probing
(loading) capacitance. The mutual capacitance which can be modeled to the first order as a lumped element capacitor
provides differentiating action. Viewing the derivative of the output signal, rise time and can be observed directly.
Through the use of probe calibration and Fourier transforms the probed signal can be re-created. Probe calibration
develops a transfer function enabling re-creation of time domain signals.
Noise is an important factor in determining the sensitivity of CMOS imagers at low light levels. Both device or transistor thermal noise and l/f noise are contributing factors, correlated double sampling reduces the effect of both thermal noise and l/f noise but is less effective in reducing l/f noise as sampling time increases. Techniques to simulate noise in sampling circuits have only recently become available and are compared here to the older analytical techniques.
Klumperink et al., have recently had a number of publications on the low frequency noise of MOSFET’s under switched gate bias conditions. Since this is an important consideration in the low frequency noise in analog circuits with switching we have investigated the experimental technique used in some detail. No consideration was given to phase noise, a mixing with and modulation of the switched bias drain current by l/f noise in the analysis of the data. This can result in a response on the spectrum analyzer which corresponds very closely to the experimental data where the switched bias off gate voltage is near the threshold voltage. If the switched bias off gate voltage is near zero however we have also found a reduction in the l/f noise at low frequencies with switched bias. Here we have also investigated the time dependence of switched bias l/f noise and have found long term transients in the time domain.
Hooge'e empirical equation has been widely used to describe l/f
or flicker noise in electron devices, where the characteristics of
different devices are represented by Hooge's parameter. There have been various explanations for l/f noise and theories used to calculate Hooge's parameter. We present here an alternative
interpretation of Hooge's empirical equation based on temperature fluctuations in electron devices. The concept of temperature fluctuations about a steady state equilibrium value is not only expected but in itself not new, temperature is only an average value. We employ a detailed balance description of heat flux to and from a heat sink and frequency dependent solutions to the diffusion equation where the high frequency variations are strongly attenuated to describe these temperature fluctuations. This method follows our previous treatment of temperature fluctuations and noise in electron
devices with high power dissipation by transmission line techniques. Temperature variations even with very low power dissipation and at thermal equilibrium can modulate the conductivity of semiconductor layers and channel's of JFET's and HEMT's. A description of Hooge's empirical equation is given by these temperature fluctuations and Hooge's parameter is shown to be simply related to the ratio of the total number of conduction electrons and total number of atoms in the sample. This new, simple and practical understand of l/f noise
suggests that appropriate heat sinks are required to minimize
l/f noise and consequently phase noise and timing jitter in high
frequency and high speed electronic systems.
Timing jitter is a concern in high speed digital integrated circuits,
the presence of timing jitter will degrade system performance in
many high-speed applications. In the first part of this paper,
we have simulated the timing jitter due to CMOS device noise in
a nine stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show the variation of absolute jitter due to flicker noise has a linear time dependence, while for white noise it has a square root time dependence, these are consistent with accepted theory. Two important parameters cycle jitter, and cycle to cycle jitter used to describe jitter performance can be obtained from simulation. Simulation results are also compared to experimental results. The
methodology developed described in this paper is also applicable to other types of clock generators and oscillators such as LC oscillators, as well as other kinds of noise sources as power supply and substrate noise. In the second part this paper, we have employed this methodology and investigated the timing jitter in silicon BJT /or SiGe HBT ECL ring oscillators, and we have shown BJT /or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. As such silicon BJT and/or SiGe HBT ring oscillators are a potential choice for low jitter applications.