Decreasing k1 factors require improved empirical models for the most critical challenge at 65nm node, contact holes especially. These requirements are reflected in the need for increasingly accurate lithography contour simulations. One of the major contributors to final OPC accuracy is the quality of the optical model. In this study, a new approach to the calibration of an optical model by using KIF will be proposed based upon the real through scanners and steppers of illumination distribution and implement to the OPC kernel.
As line width shrunk down to 90nm and below, resolution-enhanced technology in combination with thinner resists, higher NA (numerical aperture), OPC (optical proximity correction), and special mask types becomes essential for standard lower k1 lithography. Although DDL (double dipole) is popular for low k1 technology, separated x- and y-direction mask exposures will complex the process and reduce throughput. Quadrupole (Nikon) and QUASARTM (ASML) are well-known technologies for smaller pitch approaches with 45o circuit design ruled out constraints. In this paper, we report novel customized-illumination apertures for resolution-enhanced patterns and through-pitch critical dimensions control using a single exposure without design constraint and alignment problems. Both simulation and real exposure results are compared and the difference between aerial images and real resist profiles are also presented. Through-pitch CD uniformity, MEEF, line-end shortening, linearity, and DOF is improved for different illumination apertures with reduced OPC loading and cost effectively.
The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations.
Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.
Shrinkage technologies have attracted much more attention recently. The main shrinkage techniques are either to generate a thermal flow in the photo-resist with a high-temperature baking process, or to form a top layer with mixing bake treatment. In this paper, United Microelectronics Corporation (UMC) introduces a new shrinkage technology called MCTP (multiple Chemical Trim Process) and present the experimental results for our evaluation of the MCTP to implement the 90nm gate layer. Furthermore, this paper focuses on the correlation between developer process and mixing bake treatment, which has greatly benefits process window and leads to good line-edge roughness (LER) performance, especially for line-end shortening.
Planarization of gap-filling materials for low-k dual damascene processes is getting more and more important due to the photoresist process window shrinking as the pitch and critical dimensions shrink. Defects, especially pattern collapses, will become a serious problem if there is no global planarization for low-k dual damascene processes. IC manufacturers and materials vendors have proposed several ways to improve the global planarization of gap filling, such as using materials with different viscosities, fine tuning gap-filling material coating recipes, and even using optical or chemical treatments to obtain global planarization. The effect of the different conformalities of the first and second coating materials on coating performance will be discussed.