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Using pattern classification technology and a relational database, GLOBALFOUNDRIES has constructed a pattern database (PDB) of more than one million potential yield detractor patterns. In PDB, 2D geometries are clustered based on similarity criteria, such as radius and edge tolerance. Each cluster is assigned a representative pattern and a unique identifier (ID). This ID is then used as a persistent reference for linking together information such as the failure mechanism of the patterns, the process condition where the pattern is likely to fail and the number of occurrences of the pattern in a design. Patterns and their associated information are used to populate DRC Plus pattern matching libraries for design-for-manufacturing (DFM) insertion into the design flow for auto-fixing and physical verification. Patterns are used in a production-ready yield learning methodology to identify and score critical hotspot patterns. Patterns are also used to select sites for process monitoring in the fab.
In this paper, we describe the design of PDB, the methodology for identifying and analyzing patterns across multiple design and technology cycles, and the use of PDB to accelerate manufacturing process learning. One such analysis tracks the life cycle of a pattern from the first time it appears as a potential yield detractor until it is either fixed in the manufacturing process or stops appearing in design due to DFM techniques such as DRC Plus. Another such analysis systematically aggregates the results of a pattern to highlight potential yield detractors for further manufacturing process improvement.
In physical verification, DRCs represent dimensional constraints relating directly to process limitations. On the other hand, patterns represent the 2D placement of surrounding geometries that can introduce systematic process effects. It is possible to combine both DRCs and patterns in a single topological pattern representation. A topological pattern has two separate components: a bitmap representing the placement and alignment of polygon edges, and a vector of dimensional constraints. The topological pattern is unique and unambiguous; there is no code to write, and no two different ways to represent the same physical structure. Furthermore, markers aligned to the pattern can be generated to designate specific layout optimizations for improving manufacturability.
In this paper, we describe how to do systematic physical verification with just topological patterns. Common mappings between traditional design rules and topological pattern rules are presented. We describe techniques that can be used during the development of a topological rule deck such as: taking constraints defined on one rule, and systematically projecting it onto other related rules; systematically separating a single rule into two or more rules, when the single rule is not sufficient to capture manufacturability constraints; creating test layout which represents the corners of what is allowed, or not allowed by a rule; improving manufacturability by systematically changing certain patterns; and quantifying how a design uses design rules. Performance of topological pattern search is demonstrated to be production full-chip capable.
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This course provides an introduction to methodologies and techniques in Data Analytics and Machine Learning, with specific applications to semiconductor manufacturing, from physical design characterization to process and yield optimization. While the growth of (Big) Data Analytics and Machine Learning continues to increase across virtually every industrial sector, the semiconductor space has seen only a modest adoption. This course aims at lowering the entry barrier, by providing both foundational and practical skills for semiconductor engineers and practitioners. Following a comprehensive survey of the state-of-the-art and current developments in Data Analytics and Machine Learning, the course describes how functional interactions and data information flows in the Design-to-Manufacturing chain can be enhanced by analytics algorithmic methodologies.
Quantitative definitions of physical design space coverage and process space learning are introduced as the unifying abstraction, allowing for the construction of a computational application framework. Design-Technology-Co-Optimization (DTCO) is then extended with the novel paradigm of DFM-as-Search. Examples from this new DFM computational toolkit, are used to demonstrate how the advanced IC technology nodes (14, 10, 7 and 5nm) not only benefit from, but actually require the use of a new class of correlation extraction algorithms for heterogeneous data sets.
Optical proximity correction (OPC) is now a requirement for advanced semiconductor manufacturing. OPC alters the designed layout to compensate for systematic patterning distortions and/or to implement process latitude improving methods. Accurate and practical model-based OPC implementation is needed with essentially all lithography resolution enhancement techniques (RET) on complex real world designs. This practical example-oriented class will prepare attendees to implement manufacturable rule and model-based OPC on their product designs and introduce them to optimized OPC, design & process solution methods known as lithographic Design for Manufacturability (DFM).
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