In the initial stage of advanced packaging, it was applied to CSWLP (Chip-Scale-Wafer-Level-Package) mainly for the package form-factor reduction. However, advanced packaging is used not only for the package size reduction but also for many remarkable features including Fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth. Advanced packaging will also play a key role in the upcoming heterogeneous integration. Canon developed the first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. Furthermore, we will report our low distortion patterning solution of our latest packaging stepper, FPA-5520iV LF2 option.
Advanced packaging was applied during the early stages of CSWLP (Chip-Scale-Wafer-Level-Package) development for mainly package form-factor reduction. However, advanced packaging is used not only for package size reduction but also for many remarkable features including fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth computing power. Advanced packaging will also play a key role in the upcoming Chiplet era. Canon developed our first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. In addition, we study bonding error budgets for fine pitch bump package in the upcoming Chiplet era. We will compare bonding errors among Silicon interposers, Organic interposers, and Glass interposers and point out the importance of lithography tool distortion reduction to realize less than 10 µm bump pitch packages. Furthermore, we will report on our low distortion patterning solution, the FPA-5520iV LF2 advanced packaging stepper.
Demand for advanced graphics processing unit, field programmable gate array, and artificial intelligence (AI) chips continues to grow as many systems require more computing power for applications, such as AI processing and deep learning. To produce higher-performance chips, 2.5D silicon interposer technology has been developed and matured as a solution enabling high-speed data transmission between different chips, such as processors and dynamic random access memory. Increased I/O counts are required to enable higher bandwidth communication between semiconductor chips and silicon interposers can help realize higher-performance devices. Microbumps used to interconnect chips and interposers and redistribution layer must be scaled down to achieve high-density connections and next-generation devices also require larger interposers to support heterogeneous integration of multiple dies. We highlight the performance of the FPA-5520iV LF2-option stepper that is designed to provide the optimal stepper performance required for the next generation 2.5D interposers, including submicron resolution, high-accuracy mix-and-match overlay, and large field exposure.
Heterogeneous Integration is one “More-than-Moore” strategy that can help continue the trend towards overall electronics system scaling and cost reduction. Heterogeneous Integration involves high-efficiency and high-density interconnection of multiple chiplets and/or dies using advanced packaging technologies to provide communication bandwidth beyond what can be accomplished through circuit scaling alone.
This paper introduces the FPA-5520iV and FPA-8000iW steppers that are designed to meet the requirements of sub-micron Heterogeneous Integration applications. Topics include warped substrate handling, panel substrate processing, die-by-die overlay of highly distorted substrates, high-fidelity imaging across large exposure fields and high-accuracy stitching for exposure fields larger than 1 reticle.
In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology, 2.5D integration technology using silicon interposers has also become a hot topic. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool (stepper) that is now in wide use at customer sites for their most challenging processes. In this paper, Canon will explain details of FPA-5510iV features that support high-density integration. Canon will also introduce additional challenges that must be solved to ensure the success of high-density integration technologies in mass production, as well as Canon efforts to solve the remaining challenges.
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