Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography
and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion
lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the
proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography
based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is
then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the
feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach
on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP,
the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS® process is used,
realizing narrow trenches with larger DOF and less LER. For mask making, a design split is carried out, followed by
adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated
trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account
proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is
used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are
encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations
due to topography during the second litho step. For all these problems, solutions or work-arounds have been found,
After the second MHM-etch, the 50nm half-pitch pattern is transferred successfully in the underlying low-k material.
Maaike Op de Beeck, Janko Versluijs, Zsolt Tőkei, Steven Demuynck, J.-F. De Marneffe, Werner Boullart, Serge Vanhaelemeersch, Helen Zhu, Peter Cirigliano, Elizabeth Pavel, Reza Sadjadi, Jisoo Kim
Limits to the lithography process window restrict the scaling of critical IC features such as holes (contact, via) and
trenches (required for interconnects and double patterning applications). To overcome this problem, contacts or trenches
can be oversized during the exposure, followed by the application of a shrink technique. In this work, a novel shrink
process utilizing plasma-assisted polymer deposition is demonstrated: a polymer is deposited on the top and sidewalls of
photoresist by alternating deposition and etch steps, reducing the dimension of the lithography pattern in a controlled
way. Hence very small patterns can be defined with wide process latitudes. This approach is generic and has been
applied to both contacts and trenches. The feasibility of the plasma-assisted shrink technique was evaluated through
extensive SEM inspections after lithography, after shrink, and after etch, as well as through electrical evaluations.
Two-beam interference of 193nm laser light can print dense line-space patterns in photoresist, down to a resolution that can only be obtained using hyper-NA scanners, and allows for early learning on hyper-NA imaging and process development. For this purpose, a dedicated two-beam interference immersion printer, operating at 193nm wavelength, was installed in the IMEC cleanroom. The interference printer consistently generates L/S patterns at 130nm, 90nm, and 72nm pitch with exposure latitudes in the 12-26% range (when using TE-polarized light). At these pitches, process and imaging issues have been studied that are of direct interest for hyper-NA lithography. On the imaging side, we discuss the flexibility of the printer towards working with various polarizations. We show how reflection reduction strategies at the high incidence angles of hyper-NA imaging can be tested in the interference printer. On the processing side, we have screened a number of resists at 90nm pitch. A methodology to study static and dynamic leaching was developed. Several liquids with refractive index >1.6 are currently being developed as potential candidates to replace water for optical lithography at 38nm half-pitch. We have used the interference printer at 72nm pitch, with both water and liquids of refractive index 1.65.
This paper reports on an optimization methodology for BARC/resist processes in order to obtain best CD-control on various substrate topographies. A selection of resist and BARC materials is studied by means of simulations and experiments. Two BARC properties, turned out to be of major importance: planarization effects on topography and etch behavior. The topography itself is very important too: step height and lateral dimensions have a severe influence on CD control. Based on a new evaluation technique, the use of topographical swing curves, the optimum thickness of the BARC layer and of the resist layer are determined.
In this paper, the results of an NA-sigma optimization study are reported, carried out experimentally for an advanced ASML PAS5500/300 deep-UV stepper. The work has been primarily focused on a 0.25 and sub-0.25 micrometers gate layer in a logic CMOS process. A positive and negative tone resist process have been compared in terms of CD control and line- end shortening. Dry etch effects and across-field behavior has been taken into account. Furthermore the contact level of the 0.25 micrometers process have been optimized. Effects of layer dependent NA-sigma settings on overlay have been studied.
Optical proximity effects (OPE) are narrowing the process window in the 0.25micrometers - 0.18micrometers CD range. Hence optical proximity correction (OPC) might be required. These proximity effects and correction strategies are studied in detail in this work. First, an evaluation methodology is derived for the three types of OPE (linewidth differences with pitch, end-of-line effects and corner rounding). Hence, the influence of various parameters on OPE is investigated for negative tone and positive tone resists, since clear differences exist in OPE for dark field and bright field masks. Linewidth differences with pitch are small for negative tone resists, end-of-line effects are less pronounced for positive tone materials. Obviously, optical parameters have an important influence on OPE. Also, loading effects during etch processes deserve attention. Aerial image based proximity correction is evaluated. With respect to CD variations with pitch, important improvements are obtained for some resists, but not for all materials. End-of-line effects and corner rounding are improved by the use of OPC in all our experiments. Superior proximity correction results are expected with the expansion of aerial image based OPC by implementation of resist models.
Over the past several years, there have been many publications concerning the sensitivity of chemically amplified (CA) resist to substrate contamination. Resist footing phenomena are found on SiN, BPSG, TiN...etc stack films. Many approaches, such as varying the film thickness, oxide deposition, etc., have been proposed to solve this problem, with the sacrifice of increasing process complexity. In this study, we tried to improve DUV photoresist profile on TiN/AlSiCu/BPSG stacked layers. A positive tone CA resist was used and the improvement was carried out through both thin-film and lithography treatments. Since many process parameters were optimized, Taguchi design-of-experiment method was utilized to save processing cost, time and effort. The results turned out that passivation of TiN with hydrogen can improve resist footing better than either oxygen passivation or no treatment. However, the improvement was less significant than lithography process parameters. It is believed that since HMDS serves as an interlayer between TiN substrate and DUV resist, optimizing dehydration hot baking, post baking and post-exposure baking processes apparently has a more direct and significant impact on resist profile improvement than thin-film treatments. It is suggested that in this specific problem, the optimization of lithographic parameters can result in satisfactory resist profile.
Optical lithography, since many years the workhorse in manufacturing of integrated circuits, is being pushed to its limits. The extension of photolithography has been made possible by improvements in resist schemes and by resolution enhancement techniques. Although the resolution capabilities are available, maintaining CD-control will be one of the major challenges for photolithography engineers in the future. Traditionally, focus and exposure latitude are the principal criteria used in lithography. In this paper, we use an alternative method to quantify the performance of a lithographic process, based on an in-house developed software package Norman-Debora. By first modeling the CD-dependency on various input variables (focus, dose, resist thickness, reticle CD,...), Norman predicts the CD-distribution based on assumed variation intervals for these input variables. The goal of this paper is to compare the predicted CD spread by Norman with the experimentally measured CD distributions focused on the poly layer of a quarter micron CMOS process.
DUV lithography using wet developable resists can be used for the poly gate definition of 0.35micrometers CMOS processes. Four years ago, we demonstrated a resolution of 0.3micrometers L/S obtained with Shipley XP 89131 resist. Nevertheless, in order to make this and other resist processes suitable for real device applications, several problems had to be overcome. First, reflective notching and linewidth variations over steps turned out to be an important limitation. Some strategy to reduce this sensitivity to reflections has to be applied. Furthermore, in order to obtain a stable and reproducible lithographic process, process latitudes should be wide. Furthermore, a comparison between positive tone and negative tone resists is made with respect to their suitability for poly gate patterning. It was observed that negatively sloped resist profiles, as a result of the use of negative tone resists, create a controllability problem during in-line SEM inspections, and such profiles result in positively sloped poly profiles after etching. Positive tone resists have positively sloped resist profiles, but they require the use of a bright field mask, and hence reflections are much more of a problem. Also, positive tone resist are more sensitive to the delay effects.
In this new process for phase-shifting mask fabrication, molybdenum silicide (MoSi) is used as an optical shield layer and spin-on glass (SOG) as a phase-shifter layer. Chromium is employed as an etch-stopper during SOG etching. Cr etch-stopper will be removed at the end of tiie process, therefore all optical problems related to an etch-stopper are avoided. This Cr etch-stopper is also useful in inspection and repair of shifter remaining defects. At first, we will describe the fabrication process including the shifter-defect inspection and repair. Secondary, we will discuss the phase-shifting mask accuracy and its influence to the printed resist pattern when using the alternating type phase-shifting mask. Lastly,we will mention the application result of development of lithography for 64Mbit DRAM using this process.
Three types of phase-shifting mask designs are studied with respect to their suitability to print periodical L/S structures. The evaluation criteria are DOF, exposure latitude, linearity, and image contrast and slope of the intensity profile. Mask-making issues are also taken into account. The investigation is based on both simulations and experimental results. A fully transparent shifter causing an optical shift of 180 degrees is considered. A negative tone photoresist is used for the exposures with a KrF excimer laser stepper (248 nm).
The DESIRE1,2 process is based on selective silylation and subsequent dry development. A problem with silylation of resists
is the volume expansion3 of the resist image, which results in pattern deformation and displacement of small features near
large structures, also referred to as proximity effect. This lateral swel1ing45 should be reduced before implementation of
DESIRE in ULSI processes.
The effect of processing conditions, exposure wavelength, polymer composition and type of silylating agent on this swelling
phenomenon have been studied and several solutions for reducing the swelling are proposed. Both thermal and UV induced
crosslinking have been found to be a major contributor for elimination of the swelling. During silylation the silylating agent
diffuses into the resist and reacts with the hydroxyl groups of the polymer. Swelling was reduced by lowering the concentration
of these hydroxyl groups and by making use of different silylating agents with a smaller ballast group on the Si.
The DESIRE process was implemented in a 0.5 xm gatelength NMOS process, in order to examine its compatibility with
MOS processing, especially dry etch characteristics. 0.5 jim transistors have been succesfully made.
DUV lithography is an emerging technology which promises excellent resolution coupled with an
improved depth of focus. Whilst the hardware connected with this technology is rapidly maturing, there
remain question marks over the suitablilty of present DUV resists in the fabrication of actual circuits.
Two widely differing approaches are typified by Plasmask (DESIRE) which involves surface imaging and
dry development and by the wet developable Shipley Megaposit SNR 248-1.0, which utilises acid
catalysed chemistry. We have studied both materials using a contact printing system and the ASM-L PAS
5000110 DUV stepper (both at 248 nm wavelength). In particular we have compared the lithographic
performance of both resists on a variety of substrates and topographical features, commonly encountered
during processing. Practical issues such as the intrinsic adhesion, photospeed, exposure latitude, focus
latitude, linearity, thermal resistance and etch resistance are presented.
For the Shipley material we have compared its performance under various development conditions, with
respect to resolution, photospeed, profile and residues. On the Plasmask material we have investigated the
degree of silicon incorporation for various silylation conditions and for various Plasmask formulations.
Significant differences have been noted for exposures made with this wavelength (248 nm) and those
commonly reported with g and i-line exposure. Finally, the feasibility of using TMDS (1,1,3,3
Tetramethyldisilazane) as a silylating agent is presented.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.