The objective of this work is to study the possibility of implementing SOI rectennas for UWB RFIDs, with undoped Double Gate MOSFETs (DG-MOSFETs). For that purpose we use two commercial TCAD tools: Sentaurus Device (created by Synopsys), and ADS (created by Agilent) where in a large signal circuit model derived for the transistors is implemented with Verilog-A. Once the DG-MOSFETs output characteristics are fit, the rectennas performance at high frequencies is simulated; numerical and electrical results are successfully compared.
Variable capacitors, the varactors, are key components in many types of radiofrequency circuits and thus high quality
varactors are essential to achieve high quality factors in these devices.
This work presents results of a study on the variation of tuning range and quality factor when varying the depth and
separation of N+ diffusions in a PN junction varactor with fixed number of cells. For test needs four types of cells,
varying the geometry of N+ and P+ diffusions were designed. The varactors were formed by horizontally and vertically
overlapping cells. Based on their implementation structure, the varactors were divided into two groups, each comprising
4 varactors. The varactors belonging to the first group have all N+ diffusions connected to the buried layer. Varactors
from the second group use floating N+ diffusions and a buried N+ diffusion to separate pairs formed by two adjacent
Post implementation measurements show that the area of varactors from in the first and second group is 1795.74 μm2(51.9 x 34.6) and 1288.92 μm2 (46.7 x 27.6), respectively. The varactors from the 1st group have a high tuning range,
whereas the ones from the 2nd group high quality factors and require less area.
In this work, four different structures based on PN junction are studied. These structures are based on changing the
geometry of the p+ diffusion. The designed and fabricated devices will be used like integrated varactors in
radiofrequency applications. The measures have been made at frequencies since 500 MHz to 10 GHz, and the influence
that diffusion geometry has in the capacitance (C), the quality factor (Q) and the tuning range (TR) have been studied.
The pn varactors have been simulated with Taurus Device and have been fabricated in a 0.35um SiGe standard process.
In order to obtain better benefits of the varactors, the p+ and n+ diffusion geometries have been modified. This way, novel
structures called crosses, fingers, donuts, and bars have been designed and fabricated. The results of the tuning range
have been obtained superior to 40%.
This paper addresses practical considerations for the implementation of algorithms developed to increase the image resolution from a video sequence by using techniques known in the specialized literature as super-resolution (SR). In order to achieve a low-cost implementation, the algorithms have been mapped onto a previously developed video encoder architecture. By re-using such architecture and performing only slight modifications on it, the need for specific, and usually high-cost, SR hardware is avoided. This modified encoder can be used either in native compression mode or in SR mode, where SR can be used to increase the image resolution over the sensor limits or as a smart way to perform electronic zoom, avoiding the use of high-power demanding mechanical parts. Two SR algorithms are presented and compared in terms of execution time, memory usage and quality. These algorithms features are analyzed from a real-time implementation perspective. The first algorithm follows an iterative scheme while the second one is a modified version where the iterative behavioural has been broken. The video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several System on Chip (SoC) platforms are being developed.
At 0.25, 0.18 um processes and beyond important process variations occur not only from one fab to another among batches. Moreover as we approach the realm of deep-submicron design, process variations even across a single die are predicted to become a major source of spread. Reduced signal levels, noise margins and timing windows are all contributing to make previously minor variations in geometry and technological parameters a big issue for circuit design. Worse still, new mechanisms appear that cause important variations not only in transistors but also in interconnect. And some of those mechanisms, show greater variation across a single die than across similar structures on different dice from a wafer. Thus the chip designer must expect significant and not necessarily predictable differences between transistors and between interconnect resistances on a single die. Given this scenario widely recognised by process engineers, and given the additional spread built-in in the process of mapping from a soft IP design to a hard IP block, if the designer had the opportunity to know certain performance parameters of the final hard-cores without doing successive synthesis it would lead to an easier and more predictable and accurate integration of the blocks in the system. In this sense, pre-characterised trust-worthy soft-IP blocks would be preferred candidates to select. We have explored ways for quantifying and analysing the synthesis to layout spread so that, instead of modelling the spread in devices and interconnects, we model and quantify at a higher abstraction level the technology mapping process as a whole, for a set of seed designs that will give bounds and guidelines for the behaviour of other designs when they are mapped to the same technology. For that purpose, only the best-, typical-, worst-case and other process variation corners need to be known. The analysis is based in the actual measured spread of reference seed designs as they experience spread when passing from soft to hard designs.
Advances in fabrication and design technologies have contributed to integrate a complete system on a chip. A system-on-chip (SoC) is generally composed of a microprocessor core, on-chip memory and one or more specific coprocessors IPs. One of the major drawbacks of this approach is the differences in the interfaces that each virtual component (VC) of the SoC presents. The idea of a common bus infrastructure allows us to smooth the system integration and has been considered as a design solution for SoC architectures. This paper presents a review of different alternatives for SoC buses and summarizes some experiences of their use. Different alternatives exist for SoC buses. ARM has proposed AMBA (Advanced Microcontroller Bus Architecture) as an open specification that serves as a framework for SoC design. AMBA is a bus architecture multiplayer for high performance SoC designs. AMBA support multi-master configurations where a bus arbiter must be included. AMBA-Lite is a simpler alternative if you are using only one master. IBM uses CoreConnect Bus architecture as a SoC solution for buses. CoreConnect share some similarities with AMBA because both use a multilayer bus to accommodate different speeds in the system: AHB and PLB can be compared. The same situation occurs for APB and OPB. Other alternatives can be found. Wishbone is an Open Bus Specification form opencores.org that tries to solve the problem of IP integration. The idea is to specify a common interface between cores to accelerate the development of virtual components. VSIA has proposed Virtual Component Interface (VCI) as a solution to solve the problem of virtual component integration. VCI specify three types of protocols depending on the level of complexity: Peripheral, Basic and Advanced VCI. The development of the IPs compatible with any of the SoC buses above presented is a complex problem. One solution is the use of wrappers that adapts the interface of the Virtual Component to the protocol supported by the SoC buses. The two main characteristics of these wrappers are that the increased in latency and area would be as low as possible. The second solution is to design the IP with the final environment in mind.