In this paper, we present a formulation of the Sub-Resolution Assist Feature (SRAF) placement problem as a geometric optimization problem. We present three independent geometric methodologies that use the above formulation to optimize SRAF placements under mask and lithographic process constraints. Traditional rules-based methodology, are mainly one dimensional in nature. These methods, though apparently very simple, has proven to be inadequate for complex two-dimensional layouts. The methodologies presented in this paper, on the other hand, are inherently two-dimensional and attempt to maximize SRAF coverage on real and complex designs, and minimizes mask rule and lithographic violations.
Two primary tracks of DfM, one originating from physical design characterization, the other from low-k1 lithography, are described. Examples of specific DfM efforts are given and potentially conflicting layout optimization goals are pointed out. The need for an integrated DfM solution than ties together currently parallel DfM efforts of increasing sophistication and layout impact is identified and a novel DfM-enabling design flow is introduced.
One of the most compute intensive dataprep operations for 90nm PC level is the model-based optical proximity correction (MBOPC). The running time and output data size are growing unacceptably, particularly for ASICs and designs containing large macros built out of library cells (books). The reason for this growth is that the region-of-interest for MBOPC is approximately 600nm, which means that most library cells “see” interactions with adjacent books in the same row and also in adjacent rows.
In this paper, we investigate the merits of doing cellwise MBOPC. In its simplest form, the approach is to perform dataprep for each cell once per cell definition rather than once per placement. By inspection, this will reduce the computation time and output data size by a factor of P/D, where P is the number of book placements (100s to millions) and D is the number of book definitions.
Our preliminary finding indicates that there is negligible difference between nominal CD for cellwise corrected cells and chipwise corrected cells. We will present our finding in terms of average CD and contact coverage, as well as runtime reduction.
This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.
The feasibility of large scale optical proximity correction with a focus on mask manufacturability is demonstrated on the support and logic gates of a leading edge 64 Mb DRAM chip. Analysis of post reactive ion etch SEM data of the 500 - 600 nm, DUV exposed gates indicates two major contributors to across chip line width variation: first order proximity, that is, the minimum spacing to the nearest neighboring structure, and local area density or pattern loading. Data presented show a very long range (approximately equals 1 mm) impact of pattern density on post reactive ion etch line widths, favoring optical proximity correction approaches that are not based on biasing patterns to compensate for these effects. In this project, pattern density induced effects were alleviated by homogenizing the pattern loading across the chip to approximately 50% instead of biasing the gate structures to compensate for pattern density differences. Proximity induced effects were compensated for with a one- dimensional, single parameter (distance to nearest neighbor), four bucket proximity correction routine with a strong focus on mask manufacturability. Even though the unbiased 64 Mb DRAM gate level challenges mask makers with 480 MB of MEBES data, the optical proximity corrected mask posed no substantial post-processing, writing, or inspection problems in IBM's Burlington, Vermont maskhouse. A very significant 80% reduction in post reactive ion etch across chip line width variation was achieved with this corrected mask.
Hardware technology advances have dramatically reduced the cost of image computation for machine vision; unfortunately, machine vision software technology has not kept pace. This paper presents OLIVE, an object-oriented language for machine vision and image processing, intended to make it easier to develop efficient, portable applications. First, OLIVE's principal object types are defined -- IMAGEs and LOCUSes (abstractions of point sets and geometric entities) -- and their corresponding operations, including the use of LOCUSes as generalized indexes for IMAGEs. Next, a hardware architecture that simplifies the implementation while enhancing performance is discussed. Finally, the authors compare the IMAGE/LOCUS objects to the IMAGE/TEMPLATE objects of the image algebra proposed by Ritter,Wilson and Davidson.