25+ years of experience in semiconductor manufacturing industry
Current position: Technical director for ASML-imec research/studies program
Current position: Technical director for ASML-imec research/studies program
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Impact of EUV resist thickness on local critical dimension uniformities for <30 nm CD via patterning
Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.
Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.
In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition [2]. Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.
In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.
Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.
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