Nanoimprint lithography (NIL) has been received attention as an alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost, by transferring fine pattern of a template on to a resist layer by physical contact of template and resist followed by the resist curing. For more than a decade, we have been developing Jet and Flash Imprint Lithography (J-FIL) technology and challenging critical issues such as defect density, overlay, and throughput.
J-FIL is an efficient process for transferring template pattern having large variations in pattern density. However, it has the intrinsic limitation of lower throughput due to resist dispensing time prior to imprinting of every single field on the wafer and the spreading process of resist drops, slow diffusion of bubble trapped at the resist drop-boundaries. To eliminate the above mentioned steps and improve throughput, we have developed a spin coating NIL (SCN) process in which a uniform resist layer is spin coated on the entire wafer.
Identification of defect generation mechanism assuming Washburn’s model of capillary flow, has led us to optimize SCN process and thus achieving a higher throughput with lower defect density as compared to that of the J-FIL process. We will show the defect density and throughput performance of SCN process, and the possibility of introducing SCN in device production.
A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.  NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. The challenges of NIL implementation for mass-production are overlay, defects, throughput, template life, and template patterning. The overlay and defects must satisfy the requirements of the products applied. The throughput needs to provide adequate cost of ownership (CoO). Since NIL is a contact process, its template damage by the particles on a wafer is inescapable and a longer template life is required for mass production.- In our previous study, we have reported that the hp2xnm NIL process performance is getting closer to the requirement for the high volume manufacturing. We focused on the process overlay accuracy and demonstrated dramatic reduction of process overlay error by using CVA(controlled viscosity alignment) and HODC(high order distortion control) function of FPA-1200 NZ2C.  Currently, we have further developed a nanoimprint lithography (NIL) technology including NIL system, template, and resist process for half pitch 14 nm direct pattering. The hp14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer. In this paper, we report on the latest lithography performance of NIL including hp14nm pattering with single mask exposure.
A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates. NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.- In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.
Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.
A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.- In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM. In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.
A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.
Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.
Directed self-assembly (DSA) of block copolymers (BCPs) is a promising method for producing the sub-20nm features
required for future semiconductor device scaling, but many questions still surround the issue of defect levels in DSA
processes. Knowledge of the free energy associated with a defect is critical to estimating the limiting equilibrium defect
density that may be achievable in such a process. In this work, a coarse grained molecular dynamics (MD) model is used
to study the free energy of a dislocation pair defect via thermodynamic integration. MD models with realistic potentials
allow for more accurate simulations of the inherent polymer behavior without the need to guess modes of molecular
movement and without oversimplifying atomic interactions. The free energy of such a defect as a function of the Flory-
Huggins parameter (χ) and the total degree of polymerization (N) for the block copolymer is also calculated. It is found
that high pitch multiplying underlayers do not show significant decreases in defect free energy relative to a simple pitch
doubling underlayer. It is also found that χN is not the best descriptor for correlating defect free energy since
simultaneous variation in chain length (N) and χ value while maintaining a constant χN product produces significantly
different defect free energies. Instead, the defect free energy seems to be directly correlated to the χ value of the diblock
copolymer used. This means that as higher χ systems are produced and utilized for DSA, the limiting defect level will
likely decrease even though DSA processes may still operate at similar χN values to achieve ever smaller feature sizes.
Proc. SPIE. 5751, Emerging Lithographic Technologies IX
KEYWORDS: Lithography, Electron beam lithography, Backscatter, Metals, Copper, Tungsten, Monte Carlo methods, Critical dimension metrology, Electron beam direct write lithography, Semiconducting wafers
Direct write electron-beam (e-beam) lithography, which has the maskless patterning capability and the quick turnaround for new device designs and design changes, has been applied to making the engineering samples for the development of the System on Chip products (SoC). Using the e-beam lithography to the multilevel interconnect metal was known to be evaluate in view of cost and throughput. In the case of the high-energy e-beam lithography, however, the backscattered electron from the metal caused a significant proximity effect.
Authors evaluated the e-beam proximity effect using the accelerating voltage 50keV on some multi-level interconnect metal structures which consist in tungsten wiring, or Cu wiring. It was found that the backscattering range and the ratio of the backscattering energy to the incident energy depend on the thickness of metal, but also on the distance from the resist to the metal.
Therefore authors propose a new method of evaluating e-beam lithography property, concept of "EB-tree". That indicates the wafer backscatter property that has heavy metal wiring using e-beam lithography. EB-tree shows the relations of wafer backscatter range and heavy metal thickness, ratio of the backscattering energy and heavy metal thickness. EB-tree could show wafer property cause of lower levels layout, understructure metal wiring, that must be taken into account when e-beam lithography.