The current state of the art ADI overlay metrology relies on multi-wavelength uDBO techniques. Combining the wavelengths results in better robustness against process effects like process induced grating asymmetries. Overlay information is extracted in the image plane by determining the intensity asymmetry in the 1st order diffraction signals of two grating pairs with an intentional shift (bias). In this paper we discuss a next evolution in DBO targets where a target is created with multiple biases. These so called cDBO (continuous bias DBO) targets have a slightly different pitch between top and bottom grating, which has the effect of having a different bias values along the grating length and are complimentary to the uDBO technology. Where for the uDBO target, the diffraction results in a uniform Intensity pattern that carries the Overlay signal, for cDBO, an oscillating intensity pattern occurs, and the Overlay information is now captured in the phase of that pattern. Phase-based Overlay has an improved, intrinsic robustness over intensity-based overlay and can reduce the need for multi-wavelength techniques in several cases. Results on memory technology wafers confirm that the swing-curve (through-wavelength) behavior is indeed more stable for phase-based DBO target and that for accurate Overlay, this target can be qualified with a single wavelength recipe (compared to the uDBO dual wavelength recipe). In this paper, both initial results on a Micron feasibility wafer will be shown as well as demonstrated capability in a production environment.
Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay.
In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.
In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.
The target size reduction for overlay metrology is driven by the optimization of the device area. Furthermore, for the
future semiconductor nodes accurate metrology on the order of 0.2 nm is necessary locally in the device area, requiring
small in-die targets that fit within the product structures on the wafer. In this, the diffraction-based overlay metrology
using optical scatterometry is challenged to extreme limits. The small grating cannot be considered as an infinitely
repeating line-space structure with a sharply peaked spectrum, however a continuous spectrum is observed. Also,
metrology proximity effects due to the environment near the metrology target need to be taken into account. On the one
hand, this sets strict design and assembly rules of the metrology sensor. On the other hand, the optical ray-based analysis
is extended to wave-based analysis to capture the full extent of the overlay application and sensor. In this publication, the
challenges of sub-nanometer in-die overlay metrology are addressed, including measurements and simulations.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Time metrology, Chemical mechanical planarization, Scanners, Diffraction, Thin film coatings, Tin, High volume manufacturing
Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.
Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor
manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are
presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction
efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO
targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference
targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty
values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate
metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay
metrology.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning
Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of
lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay
performance is completely dependent on exposure tool.
Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies,
but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay
metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to
be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay
performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses
extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet
overlay target in DBO system.
In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification
of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields
excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on
overlay accuracy from SEM analysis.
In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer
level [1]. This drives the need for clean metrology (resolution and precision). Results have been
published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising
results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6].
But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in
addition to above-mentioned need for resolution and precision, the speed and sophistication in communication
between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling
strategy for metrology plays a big role in order to achieve this.
This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization.
For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were
used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling
scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time
contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with
the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is
used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.
mmunication between lithography and metrology is becoming increasingly demanding in advanced nodes. This is where the requirements for metrology become extremely tight. This work is dedicated to the search for "clean" metrology that is required to address these requirements. Metrology measurements are obtained via an angle-resolved scatterometry-based platform (called YieldStar). Details of the technology behind YieldStar were thoroughly discussed by Vanoppen et al. in 2010. In this current work, measurement limits are challenged to test resolution and measurement uncertainty for overlay, critical dimension (CD), and sidewall angle (focus). Results indicate an atomic-scale performance of deep subnanometers. Two different sizes of scatterometry-based overlay targets are evaluated and compared using a technique called the similarity index. A CD reconstruction model is tested for cross talk of underlying thin-film layers, specifically the case where one of the underlying layers is anisotropic. A systematic approach is taken to increase the complexity of a CD reconstruction model in steps to evaluate the capability of handling birefringence effects of anisotropic material in the model. CD metrology data (1-D and 2-D/hole layers) are compared to CD scanning electron microscope data. Focus measurements are also extended for product wafers, and focus precision is evaluated. In addition, CD metrology monitor wafer applications, such as hotplate monitoring and overlay metrology monitor wafer application for scanner stability and matched machine overlay, are tested.
Diffraction Based Overlay (DBO) metrology has been shown to have significantly reduced Total Measurement
Uncertainty (TMU) compared to Image Based Overlay (IBO), primarily due to having no measurable Tool Induced Shift
(TIS). However, the advantages of having no measurable TIS can be outweighed by increased susceptibility to WIS
(Wafer Induced Shift) caused by target damage, process non-uniformities and variations. The path to optimum DBO
performance lies in having well characterized metrology targets, which are insensitive to process non-uniformities and
variations, in combination with optimized recipes which take advantage of advanced DBO designs.
In this work we examine the impact of different degrees of process non-uniformity and target damage on DBO
measurement gratings and study their impact on overlay measurement accuracy and precision. Multiple wavelength and dual polarization scatterometry are used to characterize the DBO design performance over the range of process variation. In conclusion, we describe the robustness of DBO metrology to target damage and show how to exploit the measurement capability of a multiple wavelength, dual polarization scatterometry tool to ensure the required measurement accuracy for current and future technology nodes.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Scanners, Back end of line, Lithography, 3D metrology, Finite element methods, Scatterometry, Critical dimension metrology
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput).
Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at
ASML. Authors have already published results of a thorough investigation of this promising new metrology
technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and
advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from
YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications.
Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.
KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scanners, Lithography, Back end of line, Metals, Scatterometry, Front end of line, Signal to noise ratio
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level [4].
Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have
already published results of a thorough investigation of this promising new metrology technique which showed
excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for
CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform.
This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus)
and product wafer applications.
A new metrology technique is being evaluated to address the need for accuracy, precision, speed and sophistication in metrology in near-future lithography. Attention must be paid to these stringent requirements as the current metrology capabilities may not be sufficient to support these near future needs. Sub-nanometer requirements in accuracy and precision along with the demand for increase in sampling triggers the need for such evaluation.
This is a continuation of the work published at SPIE Asia conference, 2008. In this technical presentation the authors would like to continue on reporting the newest results from this evaluation of such technology, a new scatterometry based platform under development at ASML, which has the potential to support the future needs.
Extensive data collection and tests are ongoing for both CD and overlay. Previous data showed overlay performance on production layers [1] that meet 22 nm node requirements. The new data discussed in this presentation is from further investigation on more process robust overlay targets and smaller target designs. Initial
CD evaluation data is also discussed.
Need for accuracy, precision, speed and sophistication in metrology has increased tremendously over the past few
years. Lithography performance will increasingly depend on post patterning metrology and this dependency will
be heavily accelerated by technology shrinkage. These requirements will soon become so stringent that the
current metrology capabilities may not be sufficient to support these near future needs. Accuracy and precision
requirements approaching well into sub-nanometer range while the demand for increase in sampling also
continues, triggering the need for a new technology in this area.
In this technical presentation the authors would like to evaluate such technology that has the potential to support
the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Data on first order
diffraction based overlay shows unprecedented measurement precision. The levels of precision are so low that for
evaluation special methods has been developed and tested. In this paper overlay measurement method and data
will be discussed, as well as applicability for future nodes and novel lithography techniques. CD data will be
reported in the future technical publications.
The use of backscatter electron detection in a wafer alignment system has been investigated. For certain types of wafer processing such an alignment system might show improved process robustness compared to optical sensors. This expectation is based on the principle that the alignment signal generated by backscattered electrons is formed by probing the volume of the alignment mark rather than its surface. This paper presents both simulations and experiment results on the viability and potential physical limitations of this alignment method. Physical properties of the backscatter electron alignment system are discussed. The results confirm that for some semiconductor wafer processes, this concept lives up to the expectations. The impact of electron beam energy, shot noise and alignment mark surface
roughness on process-induced alignment shift and aligned position
repeatability is investigated. In addition, the sensitivity to magnetic fields and mechanical vibrations has been investigated. The theoretically predicted relation between repeatability and illumination dose, due to shot noise has been experimentally confirmed. The results show that backscatter electron alignment is a promising alignment method, although a few issues remain unresolved.
A spectroscopic, diffraction based technique is proposed in this paper as an alternative solution for overlay metrology in technology nodes below 90 nanometers. This novel technique extracts alignment error from broadband diffraction efficiency of specially designed diffraction targets in real-time. Feasibility of the technique is studied for a front-end process flow by measuring grating targets printed on a series of wafers which were intentionally mis-processed to introduce inter-die (grid) level programmed overlay errors. Correlation to conventional imaging overlay measurements is demonstrated. Short term and long term data sets demonstrate sub-half-nanometer in 3-sigma statistical parameters that characterize the diffraction overlay system, repeatability, reproducibility, Tool-Induced-Shift and tool-to-tool matching. The resulting total measurement uncertainty for this technique is thus demonstrated to be in the sub-nanometer range.
Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.
Advances in wafer processing techniques and the increase of wafer size to 300 mm present new challenges to overlay performance. This paper focuses on advances n the area of process-induced alignment accuracy using the ASML ATHENA alignment system. In the experiments, process variations were deliberately increased to characterize the influence of process-tool settings on wafer alignment performance. In the STI process flow, overlays of <32 nm on marks in silicon or marks in the STI layer have been achieved. In the back-end-of-line, aluminum layers exhibit a significant shift of alignment marks and off-line metrology targets. A geometrical model of the sputter tool is used to explain the origin of this effect. Possible improvements in process corrections are indicated. For the copper dual damascene process investigated here, the dielectrics are non-absorbing. Overlays of 25 nm on marks in silicon and 29 nm on marks in the metal layer are obtained. On 300 mm wafers, a new measurement method is capable of measuring process effects to an accuracy within 6.2 (3(sigma) ). This method is used to measure resist spin effects.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.