We report a 20 nm half-pitch self-aligned double patterning (SADPP) process based on a resist-core approach. Line/space 20/20 nm features in silicon are successfully obtained with CDvariation, LWR and LER of 0.7 nm, 2.4 nm and 2.3 nm respectively. The LWR and LER are characterized at each technological step of the process using a power spectral density fitting method, which allows a spectral analysis of the roughness and the determination of unbiased roughness values. Although the SADP concept generates two asymmetric populations of lines, the final LLWR and LER are similar. We show that this SADP process allows to decrease significantly the LWR and the LER of about 62% and 48% compared to the initial photoresist patterns. This study also demonstrates that SADP is a very powerful concept to decrease CD uniformity and LWR especially in its low-frequency components to reach sub-20 nm node requirements. However, LER low-frequency components are still high and remain a key issue tot address for an optimized integration.
Pulsed plasmas have been proposed many years ago by research labs and have shown a great potential for etch process improvement. Nevertheless, they have been introduced in manufacturing only recently and the exact characteristics of pulsed plasmas in industrial scale reactors are hardly known. In this paper, we have characterized silicon etching in pulsed HBr/O2 plasmas using advanced plasma diagnostics (mass spectrometry and ion flux probe) in a 300 mm industrial reactor. We show that pulsing the plasma at low duty cycle reduces the gas molecules dissociation and plasma temperature, as well as the flux of energetic ions to the wafer. The ions during silicon etching are mostly silicon-containing ions that are heavier at low duty cycle. Silicon patterns etched using pulsed plasmas present improved profiles, which is attributed to more uniform passivation layers at low duty cycle.
The best strategy to transfer nanopatterns formed from the self assembly of PS/PMMA bloc copolymers into a silicon
substrate is investigated. We show that a hard mask patterning strategy combined with a plasma cure treatment of the PS
mask are necessary to reproduce the PS mask pattern into the silicon with a good critical dimension control. In addition,
typical silicon etching plasma condition must be revisited to allow the etching of sub-20 nm holes. These results indicate
that block copolymer can be readily used as etching masks for advanced CMOS technology.
Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex
stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully
addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are
limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized
pulsed ICP technologies and their potential benefits for front end etch process performance.
The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is
analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas
stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.
Conference Committee Involvement (11)
Advanced Etch Technology and Process Integration for Nanopatterning XI
27 February 2022 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning X
22 February 2021 | Online Only, California, United States
Advanced Etch Technology for Nanopatterning IX
25 February 2020 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VIII
25 February 2019 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VII
26 February 2018 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VI
27 February 2017 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning V
22 February 2016 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning IV
23 February 2015 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning III
24 February 2014 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning II
25 February 2013 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning
13 February 2012 | San Jose, California, United States