Speckle can be reduced through increased laser bandwidth co-optimized with SMO-OPC. Figure 1 is a plot of calculated speckle contrast for the Cymer 860ix laser that is coupled with the ASML NXT 2000 scanner and the Cymer 960ix coupled with the ASML NXT 2050 scanner with the increased pulse duration (TIS is time integral squared) vs laser bandwidth. We focus on 300fm speckle contrast for the XLR 960ix (blue) and the XLR 860ix (red) at 640fm, where the speckle contrast is equal which is a reduction of 30%. On wafer LWR vs laser bandwidth for a 56nm line on a 120nm pitch test case data has been generated. This case was used in the qualification of the pulse stretcher2. Wafers have been processed with a fixed imaging pupil and mask CD with increasing laser bandwidth. This data will be reviewed, to demonstrate a reduction in local critical dimension uniformity (LCDU). The Authors will review simulations, experimental data and the process to develop a working imaging solution that further reduces LCDU.
Extreme ultraviolet (EUV) technology enables further downscaling for logic and memory designs. This powerful technology comes with new challenges that must be controlled to unlock the novel technology accuracy and capabilities. Freeform (curvilinear) masks introduce a flexible tape-out capability that enables customers to realize EUV technology accuracy and capabilities on wafer. However, the accuracy enhancements of curvilinear masks do not come free of challenges. Source optimization, optical proximity correction (OPC) and verification runtime, mask proximity correction (MPC) runtime, data volume handling at fracture, and finally mask writing time are some of these challenges. In this paper, we present an affordable runtime tape-out flow for optical proximity correction and verification. This tapeout flow connects the capabilities of different engines to balance accuracy and mask turnaround time. Combining the benefits of rigorous solvers and pattern matching with affordable OPC, mask rule check (MRC) and verification capabilities cut down mask turnaround time from weeks to days, offering customers cutting edge technology on wafers with acceptable runtime. In this paper, we present a new flow for EUV freeform OPC with demonstrated runtime and accuracy benefits validated on wafer
Despite being crucial in an optical lithography process, “dose” has remained a relative concept in the computational lithography regime. It usually takes the form of a percentage deviation from a pre-identified “nominal condition” under the same illumination shape. Dose comparison between different illumination shapes has never been rigorously defined and modeled in numerical simulation to date. On the other hand, the exposure-limited nature of EUV lithography throughput demands the * illumination shape being optimized with the physical dose impact consciously taken into consideration. When the projection pupil is significantly obscured (as in the ASML EXE high NA scanner series), the lack of a proper physical dose constraint may lead to suboptimal energy utilization during exposure. In this paper, we demonstrate a method to accurately model the physical dose in an optical lithography process. The resultant dose concept remains meaningful in the context of a changing illumination pupil, which enables co-optimization of imaging quality and a throughput metric during the Source-Mask Optimization (SMO) phase, known as the Dose-Aware SMO. With a few realistic test cases we demonstrate the capability of Dose-Aware SMO in terms of improving EUV throughput via reducing the effective exposure time, in both regular and obscured projection systems. The physical dose modeling capability in computational lithography not only addresses those immediate challenges emergent from EUV throughput, but also opens the gate towards a broad class of exciting topics that are built upon physical dose, such as optical stochastic phenomena and so on.
With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.
Advancing technology nodes in CMOS Image Sensors (CIS) continues to drive a shrinking process to acquire higher resolution and low power consumption as well as more cost-effective production. With the sensor pixel size scaling down, a thicker photoresist (with aspect ratios greater than 10:1) is introduced to block high-energy implants with extremely localized implant profiles. Then double exposures/double focus (DE/DF) is applied to make sure the resist profile and process window is comparable or better. However, this process is a big challenge at high volume manufacturing (HVM) phase because of throughput loss. To recover it due to DE/DF, we invented SE MFI which uses two wavelengths (“colors”) generated by the KrF excimer laser to solve the problem. Due to the chromatic aberrations in the lens, the focal plane shift of different wavelength produces nearly the same result as DE/DF. However, the use of two-wavelengths brings some challenges. The first is the loss of image contrast and the second is the impact of chromatic aberrations across the slit which results in image shift and image asymmetry. In this work, we demonstrated that the use of ASML’s Tachyon KrF MFI source mask optimization (SMO) that can match the MFI SE process to DE/DF process of record (POR). We first used Tachyon Focus-Exposure Modeling plus (FEM+) to calibrate a DE resist model by using DE POR wafer data. Then we converted the DE model to a SE MFI model. At the end, we use the Tachyon MFI-SMO to optimize the SE MFI to match the DE/DF and MFI sidewall profiles through process window conditions at the center slit. We achieved making the MFI and DE/DF sidewall difference significantly smaller than other noises which can be measured on wafer at the center slit. We evaluated the chromatic aberration impact on through slit sidewall profiles also meet the specification. The through slit matching between MFI and DE/DF was further improved by through-slit mask optimization. This is done by inserting asymmetry sub resolution assist features (SRAFs). Tachyon Optical Proximity Correction plus (OPC+) can support full chip mask corrections for full-chip HVM. The above MFI technology including Tachyon optimization capability will be verified by wafer exposure via comparison between MFI and DE wafer results.
Over the years, lithography engineers have continued to focus on CD control, overlay and process capability to meet node requirements for yield and device performance. Previous work by Fukuda1 developed a multi-exposure technique at multi-focus positions to image contact holes with adequate DOF. Lalovic2 demonstrated a fixed 2-wavelength technique to improve DOF called RELAX. The concept of multi-focal imaging (MFI) was introduced3 demonstrating two focal positions are created that are averaged over the exposure field, this wavelength “dithering” approach which can be turned on and off, thus eliminating any potential scanner calibration issues.
In this work, the application of this imaging method (1 exposure-2 focus positions) can be used in thick photoresist and high aspect ratio applications. An example of thick photoresist imaging is shown in figure 1. We demonstrate 5um line and space features in 10um of photoresist at 3 different imaging conditions. On the left, single focus imaging (SFI) at best dose and focus, the center image which is also SFI but at a defocus of +3.2um. On the right is MFI with 2 focus positions of 0 and 2.8um. Here we can see a significant improvement in the SWA linearity and image profile quality. A second example of high aspect ratio imaging using MFI is shown in figure 2. The aspect ratio of 13:1 is shown for this. The use of Tachyon KrF MFI source – mask optimization flow will be reviewed to demonstrate optimum conditions to achieve Customer required imaging to meet specific layer requirements.
EUV lithography is uniquely positioned to extend single exposure solutions for critical imaging layers at the 7 nm technology node and beyond. In this work, we demonstrate the application of advanced EUV resolution enhancement techniques to enable bidirectional printing of 36 and 32 nm pitch standard logic cell and SRAM designs with 0.33 NA optics using an EUV OPC model. Prior work has highlighted the issues of pattern placement errors and image contrast loss due to the non-telecentricity that is inherent in EUV reflective imaging systems and masks. This work has also demonstrated utilizing asymmetric pupil to reduce the pattern placement error. It has been previously shown that there is a potential reduction in common process window due to through-pitch best focus shifts with non-optimized SRAF placement. In this paper, we demonstrate the use of: pattern placement error aware SMO, asymmetric illumination shape, and SRAF placement optimization to increase the overall common process window by as much as 40% compared to OPC only optimization. Consequently, we demonstrate the improved post-RET single patterning solution for 0.33 NA EUV bi-directional 7 nm node logic designs. We show that these techniques can achieve the required performance for MEEF, best focus shift across features, and ILS, which is known to be important for reducing stochastics and subsequent line-edge-roughness (LER).
Early in a semiconductor node’s process development cycle, the technology definition is locked down using somewhat risky assumptions on what the process can deliver once it matures. In this early phase of the development cycle, detailed design rules start to be codified while the wafer patterning process is still being fine-tuned. As the process moves along the development cycle, and wafer processes are dialed-in, key yield improvement efforts focus on variability reduction. Design retargeting definitions are tweaked and finalized, and the use of finely tuned etch models to compensate for process bias are applied to accurately capture the more mature wafer process. The resulting mature patterning process is quite different from the one developed during the early stages of the technology definition. In this paper we describe an approach and flow to drive continuous improvement in the mask solution (OPC and MBSRAF) later in the process development and production readiness cycle stage. First, we establish the process window entitlement within the design-space by utilizing advanced mask optimization (MO) combined with the baseline process (i.e., model, etch compensation, and design retargeting). Second, gaps to the entitlement are used to identify and target issues with the existing OPC recipe and to drive continuous improvements to close these performance gaps across the critical design rules. We demonstrate this flow on a 20 nm contact layer.
Negative tone development (NTD) processes have been widely explored as a way to enhance the printability of
dark field features such as contact holes and trenches. A key consequence of implementing NTD processes and
subsequent tone reversal of dark field reticles is the significantly higher transmission of bright field masks and thus
higher light intensity in the projection optics. This large increase in mask transmission coupled with the higher
throughput requirements of multiple patterning and the use of freeform illumination created by source mask
optimization creates a significant amount of lens heating induced aberrations that must be characterized and
mitigated. In this paper, we examine the lens heating induced aberrations for high transmission reticles common
to NTD using both simulations and experiments on a 193 immersion lithography tool. We observe a substantial
amount of aberrations as described by even and odd order Zernike drifts during the course of a wafer exposure lot.
These Zernike drifts per lot are demonstrated to have the following lithographic effects: critical dimension shifts,
pitch dependent best focus shifts and image placement errors between coarse and fine patterned features. Lastly,
mitigation strategies are demonstrated using various controllers and lens manipulators, including FlexWave with
full Zernike control up to Z64, to substantially reduce the lens heating effects observed on-wafer.
Silicon is the primary material used for the fabrication of solar cells and it is responsible for about 40% of
the cost. Metamaterials show promise in enhancing the performance of silicon solar cells thus, improving the
efficiency. Here we report on the fabrication of a broadband, antireflective, conductive metamaterial capable
of channeling light into a solar cell. As a precursor to making the metamaterial, standard p-n junctions were
fabricated. Conventional phosphorus oxychloride (POCl3) furnace diffusion was used to create the p-n junction.
When the p-n junction was forward biased, the measured current exhibited a diode characteristic. The measured
photocurrent response yielded an open circuit voltage for the p-n junction at 0.48 VDC. The metamaterial
film was fabricated, placed atop the p-n junction and characterized. Initial tests showed that the metamaterial
antireflective properties were on par with those of standard industrial single-layer silicon nitride coatings. Further
testing is being performed to assess the full optical and electrical performance of the metamaterial film.
As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in
collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the
manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes,
alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting
16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity
(CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are
also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel
overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure
(CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction
method. The effects of the exposure field size are also compared between a small field and the full field. Included in all
the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.
As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical
aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning
techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed
DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split
patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO
baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In
this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for
our DETO process.
Computational lithography (CL) is becoming more and more of a fundamental enabler of advanced semiconductor
processing technology, and new requirements for CL models are arising from new applications such as model-based
process tuning. In this paper we study the impact of realistic machine parameters that can be incorporated in a modern
CL model, and provide an experimental assessment of model improvements with respect to prediction of scanner tuning
effects. The data demonstrates improved model accuracy and prediction by inclusion of scanner-type specific modeling
capabilities and machine data in the CL model building process. In addition to scanner effects, we study laser bandwidth
tuning effects and the accuracy of corresponding model predictions by comparison against experimental data. The data
demonstrate that the models predict well wafer CD variations resulting from laser BW tuning. We also find that using
realistic spectral density distribution of the laser can provide more accurate results than the commonly assumed modified
Lorentzian line shape.
Double patterning is considered the most viable option for 32- and 22-nm complementary metal-oxide semiconductor (CMOS) node development and has seen a surge of interest due to the remaining challenges of next-generation lithography systems. Most double patterning approaches previously described require intermediate processing steps (e.g., hard mask etching, resist freezing, spacer material deposition, etc.). These additional steps can add significantly to the cost of producing the double pattern. Alternative litho-only double patterning processes are investigated to achieve a composite image without the need for intermediate processing steps. A comparative study between positive–negative (TArF-P6239+N3007) and positive–positive tone (TArF-P6239+PP002) imaging is described. In brief, the positive–positive tone approach is found to be a superior solution due to a variety of considerations.
The fragile nature of alumina and the intrinsic Al2O3 barrier layer at the pore bases has hindered its use in optoelectronic
devices. In this work, these issues have been addressed by the development of a nanoporous alumina template directly on
a silicon substrate with platinum electrodes at the pore bases. This template was then used to perform dc galvanostatic
electrochemical deposition of II-VI semiconductor heterostructure nanowires that were then used to fabricate pixilated
detector arrays.
The challenge for the upcoming full-chip CD uniformity (CDU) control at 32nm and 22nm nodes is unprecedented with
expected specifications never before attempted in semiconductor manufacturing. To achieve these requirements, OPC
models not only must be accurate for full-chip process window characterization for fine-tuning and matching of the
existing processes and exposure tools, but also be trust-worthy and predictive to enable processes to be developed in
advance of next-generation photomasks, exposure tools, and resists. This new OPC requirement extends beyond the
intended application scope for behavior-lumped models. Instead, separable OPC models are better suited, such that each
model stage represents the physics and chemistry more completely in order to maintain reliable prediction accuracy. The
resist, imaging tool, and mask models must each stand independently, allowing existing resist and mask models to be
combined with new optics models based on exposure settings other than the one calibrated previously.
In this paper, we assess multiple sets of experimental data that demonstrate the ability of the TachyonTM FEM (focus and
exposure modeling) to separate the modeling of mask, optics, and resists. We examine the predictability improvements
of using 3D mask models to replace thin mask model and the use of measured illumination source versus top-hat types.
Our experimental wafer printing results show that OPC models calibrated in FEM to one optical setting can be
extrapolated to different optical settings, with prediction accuracy commensurate with the calibration accuracy. We see
up to 45% improvement with the measured illumination source, and up to 30% improvement with 3D mask.
Additionally, we observe evidence of thin mask resist models that are compensating for 3D mask effect in our wafer data
by as much as 60%.
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
With 32nm and 22nm feature size node in the near future, Double patterning type processing will be in
mainstream device manufacturing in most cutting edge Fabrication facilities. These type of processes
requires cooperation between the litho cell and the other processing modules. In a collaboration
between ASML and TEL we have developed a integrated solution to image 30nm Contacts. We
describe a novel technique to achieve a geometric shrink from a starting geometry of 65nm down to the
final feature size of 30nm for each of the two contact images Processing 2 images separately could
produce two distinct populations for alignment and critical dimensions. We will show the ability to
image 65nm contacts on a 130nm pitch with acceptable process windows and then apply the novel CD
shrink process to shrink the 65nm contacts to 30nm final dimension. The second level of contacts is
imaged in between the 1st set of contacts allowing us to image a 32nm ½ pitch contact pattern.
We show the ability to Image 2 separate sets of contacts using a split clip layout with a single
distribution for critical output parameters. We address the following process challenges:
1) Overlay capability across the slit and across the field.
2) Critical Dimension capability across the slit and across the Field.
3) Sidewall angle integrity with acceptable process window.
Using the novel CD shrink process TEL has developed and imaging capability of the an ASML 1700i
TWINSCAN, we can achieve a double pattern contact process with acceptable process capability.
The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC.
To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.
The objective of this work is to demonstrate a simple Linear Superposition approach to creating an optimized illumination scheme from commonly available apertures (e.g. conventional, annular, quadrupole, dipole, etc.) that meet a variety of lithographic process metrics. Previous authors have demonstrated a variety of approaches to optimize the illumination for a given lithographic process. One common example is to use an optimized illumination for a specific pitch range and breaking the exposure into multiple reticles designed to print only nested or isolated features. A second example that has been widely demonstrated is to develop a single custom illuminator, which requires long lead times for delivery and a large capital investment. The true on-wafer performance of this custom illuminator can only be determined post-installation, providing limited ability to verify the simulation work a priori. The linear superposition method described here produces an optimal illumination scheme for a given photolithographic process. The success of this approach is due to the acceptably small nature of the electric field interaction terms between individual illumination modes allowing a multiple-exposure system to model a composite source. Images from optimized sub-components can be added to generate a composite image that is superior overall to any one process alone. After each exposure in a multiple exposure system there is a latent image that is only developable after a specific energy or dose level has been surpassed. It is the additive process of these latent images that creates the composite image. The composite image has the additive properties of the sub-components according to their dose fractions. Once the optimal process and dose split have been determined, it is straightforward to create a composite aperture to produce the same process by a single exposure. The composite aperture is the addition of the multiple sub-components with the relative transmission of each related to the illuminated surface area for systems designed to deliver uniform brightness. This approach produces superior pattern fidelity and an optimized common lithography process without the pitfalls of any one of the sub-component illumination modes.
A nanoporous alumina template made from a multilayer metal film structure has been developed that allows for the in situ removal of the electrically insulating alumina barrier layer, exposing a Pt electrode at the pore bases. This barrier free nanoporous system has great potential for DC electrodeposition of a wide variety of materials in the alumina pores. The nanoporous template is fabricated in a more practical way than existing techniques and can be used for the fabrication of nanowires of many materials. Because the template is fabricated directly on the final substrate, no film transfer technique is needed and the substrate can include electrical circuitry. A silicon substrate may be used that provides mechanical stability, facilitates processing, and allows integration with IC components. This will allow for cheap and high efficiency infrared detectors to be fabricated in a practical and cost effective way. The quantum wire devices fabricated in this way can be customized to be used as infrared sensors at a variety of infrared wavelengths.
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