Dr. Goldstein received his Ph.D. in physics from Dartmouth College and completed postdoctoral research there before joining Intel Corporation where he worked for 20-years in a variety of roles in advanced semiconductor lithography research, pathfinding, and technology development. Most of the two decade period was as a Sr. Principal Engineer (Physicist), where he worked on research with suppliers including ASML, Zeiss, and Nikon. He was a front end critical-layer immersion lithography tool owner in Intel’s leading development fab; ran a group that translated process technology requirements into equipment specifications and acceptance testing methods; and, was the founding program manager of SEMATECH’s EUV Mask Infrastructure (EMI) partnership with Zeiss, TSMC, Samsung, Intel, GLOBALFOUNDRIES, and SK Hynix. He initiated Intel's first EUV Pellicle project, and was the lead optical designer on several EUV optical design efforts including the EUV Micro Exposure Tool (MET5) which is in operation at Lawrence Berkeley National Laboratory, along with several other EUV source, metrology, and lithography projects. He has an extensive background in the challenges related to bringing up a new and high yielding manufacturing process technology. Although Dr. Goldstein still consults on lithography and optical design, he founded Rx Analytic (www.rxanalytic.com) which is an early stage nanopharmaceutical company. The platform technology was developing a next generation pharmaceutical carrier for highly precise and efficient delivery of compounds into the small airways of the lungs with in-vivo control of drug release kinetics. Dr. Goldstein is a physicist and applied mathematician with a record of identifying novel opportunities and solving important problems.
Projection optics for extreme ultraviolet lithography (EUVL) micro-field exposure tools (METs) with a numerical aperture of 0.5
Comparison of techniques to measure the point spread function due to scatter and flare in EUV lithography systems
Determination of the flare specification and methods to meet the CD control requirements for the 32-nm node using EUVL