Both the active column sensor (ACS) pixel sensing technology and the PVS-Bus multiplexer technology have been applied to a color imaging array to produce an extraordinarily high resolution, color imager of greater than 8 million pixels with image quality and speed suitable for a broad range of applications including digital cinema, broadcast video and security/surveillance. The imager has been realized in a standard 0.5 μm CMOS technology using double-poly and triple metal (DP3M) construction and features a pixel size of 7.5 μm by 7.5 μm. Mask level stitching enables the construction of a high quality, low dark current imager having an array size of 16.2 mm by 28.8 mm. The image array aspect ratio is 16:9 with a diagonal of 33 mm making it suitable for HDTV applications using optics designed for 35 mm still photography. A high modulation transfer function (MTF) is maintained by utilizing micro lenses along with an RGB Bayer pattern color filter array. The frame rate of 30 frames/s in progressive mode is achieved using the PVS-Bus technology with eight output ports, which corresponds to an overall pixel rate of 248 M-pixel per second. High dynamic range and low fixed pattern noise are achieved by combining photodiode pixels with the ACS pixel sensing technology and a modified correlated double-sampling (CDS) technique. Exposure time can be programmed by the user from a full frame of integration to as low as a single line of integration in steps of 14.8 μs. The output gain is programmable from 0dB to +12dB in 256 steps; the output offset is also programmable over a range of 765 mV in 256 steps. This QuadHDTV imager has been delivered to customers and has been demonstrated in a prototype camera that provides full resolution video with all image processing on board. The prototype camera operates at 2160p24, 2160p30 and 2160i60.
A family of monochrome, high-speed linear imagers has been developed with each device to be available as a single chip fabricated using a standard commercially available CMOS process. Currently, the 2048 pixel device has been fabricated using a 0.5-micron CMOS process and its architecture, functionality and performance is described. The family of imagers features a unique combination of high functional integration, very high speed, low dark current, high sensitivity and high pixel-to-pixel uniformity. The pixels are 7.0 microns by 7.0 microns and have 100 percent fill factor. The high pixel-pixel uniformity is made possible by using low dark current pixels, a correlated double sampler circuit per pixel and a fully differential video bus. High functional integration is enabled by on-chip logic that is provided to minimize support circuitry and simplify application. Included are several exposure modes that provide full-frame electronic shutter, independent control of integration time and simultaneous integration and read-out. Only 5 volts DC and clock signal running at twice the desired pixel rate are required for basic operation. Low dark current and high sensitivity result from a novel pixel and low-noise preamplifier structure. A novel video multiplexing structure provides the very high read-out speed of 60 Mpixel/sec per 2048 pixel segment while sustaining an MTF of 50 percent at 35 line pairs per millimeter.
This paper describes a new improved method of employing an amplifier per pixel that eliminates FET threshold and gain variations problems of prior art. Existing amplifier per pixel designs utilizes 3 or 4 FETs per pixel and the amplifier consists of a source follower. The source follower is problematic in 2D arrays due to threshold variations and resulting gain variations per pixel causing extensive peripheral circuitry and/or software to correct. The active column sensor employs a true unity gain amplifier per pixel, eliminating threshold and gain variations. The simplified pixel electronics allow for smaller and/or more sensitive pixels and always at lower cost through improved yields. Disclosure of 1.5 FET double poly, 1.5 FET single poly, and photodiode configurations and with result on various pixels.
A high-speed 512 X 512 charge injection device with selectable one to four video ports has been developed, fabricated, and tested beyond the designed speed of operation. The imager has four independently controllable video ports allowing for all possible combinations. This is accomplished by having each port hard wired to one out of every four rows sequentially. Each port is selected via a multiplexer in the sequence desired. The horizontal scanner was designed to operate up to 30 MHz. The device was tested at the wafer level to 42 Mhz element rate per port. This element rate allows a maximum of 168 MHz element rate with four ports operating in parallel.