The effects of EUV scanner actuated overlay corrections on image fidelity are discussed. Intrafield overlay corrections are implemented by reticle and/or wafer stage modulations during the exposure scan, which may lead to stage desynchronizations. The impact of such a mismatch on imaging is comparable to stage vibrations, which contribute to image blurring commonly known as image fading. For this study, deliberate stage desynchronizations were introduced by means of an asymmetric image rotation and effects on image fidelity qualitatively evaluated by pattern shift response (PSR) metrology. The PSR targets studied are blossom-style marks with asymmetric petal designs that transform process variations to a virtual pattern shift, which can be measured by conventional image-based overlay metrology. Corroborating as well as quantitative results were acquired by analyses of line width roughness. It was found that stage desynchronizations induced by overlay corrections can significantly degrade image fidelity starting with increased line width roughness up to a total pattern failure of linewidths relevant to current and future technology nodes. PSR metrology shows excellent capabilities to characterize relative image fidelity as well as across slit distortions and is therefore a suitable monitoring technique for on-wafer performance.
Although lens aberrations in EUV imaging systems are very small, aberration impacts on pattern placement error and overlay error need to be carefully investigated to obtain the most robust lithography process for high volume manufacturing. Instead of focusing entirely on pattern placement errors in the context of a single lithographic process, we holistically study the interaction between two sequential lithographic layers affected by evolving aberration wavefronts, calculate aberration induced overlay error, and explore new strategies to improve overlay.
An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed.
In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.
Gate patterning has always been held to tight specifications for CD variation compared to other layers. Specifically, the gate layer is more concerned with the total CD variations including Across Chip Linewidth Variation (ACLV), Across Wafer Linewidth Variation (AWLV), CD variation through pitch (Proximity bias), than other layers. Therefore, complementary phase shift (c:PSM) imaging has been introduced at the gate layer under the assumption that it will reduce the total CD variation compared to binary imaging. However, c:PSM data conversion of random logic can introduce additional biases that also impact CD control. These new biases include CD variation as a function of shadow size, reticle-to-reticle overlay error, shifter width, and shifter height (a function of the transistor width and the shifter extension). This paper will show the improvements in ACLV and AWLV using c:PSM. This paper will also look at the increase in the proximity bias for c:PSM compared to binary imaging and show results for implementing a 1-D OPC correction on the phase shift reticle. In addition, this paper will also look at the magnitude of the various additional c:PSM biases mentioned. This paper will discuss the interaction of the different phase shift conversion input parameters for complex random logic and the limitations they impose on how tight we can make the final CD distribution. Finally, since c:PSM allows for selective sizing of CDs over active and over field, a brief discussion will also be given for the CD control of the complementary binary reticle.
Standardizing on reticle size is critical for semiconductor tool manufacturers and the semiconductor industry as a whole. The advantages of large reticles are well known: larger die and increased throughput. Although predictions of extremely large die have not yet been realized, the throughput implications remain valid. As large reticles have the potential to increase throughput, some proponents view them as potential cost savers. This work examines the implications of migrating from today's standard 6-inch reticles to 9-inch reticles. It explores the factors that drive reticle cost, and describes why larger reticles should cost more. The paper also describes the cost benefit of implementing larger masks. Comparing the expected cost of building the reticle to the potential cost savings of using the reticle in production provides significant insight into the problem of selecting the optimal reticle size. Finally, the paper presents an analysis of the impact of 6X reduction systems on the selection of reticle size.
It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.
It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.
This paper uses simulation and experiment to study near resolution limit patterning of contacts and damascene trenches using conventional i-line lithography. Special attention is paid to the requirements for substrate control. The patterning behavior is compared to DUV lithography results. We also evaluate the cost-of-process for an i-line process using substrate and optical enhancements compared to a standard 248 nm DUV process.
Reticle cleanliness is becoming an ever more serious issue in today's sub-micron wafer fabrication facilities. Line-widths on reticle are at or pushing below one micron. The defined size of what is a "killer' defect has shrunk accordingly. The small particulates added in shipping, reticle storage, and reticle handling are having a much greater impact on device yield. Current methods of reticle protection and storage are proving inadequate in preventing an accumulation of particles that would previously have been considered inconsequential. Device yield as a function of reticle cleanliness has become a major concern. Cost and turn time also factor into the need for improved reticle protection and handling methods. The cost for a super high-end reticle has sky-rocketed into the 5 figure range for a "traditional" binary, chrome-onquartz photomask. Holding up a wafer lot for what can be a two week replacement turn-time on critical spec reticles can result in catastrophic delays to production. Protection of these manufacturing critical resources is an absolute necessity. As a result of these issues, increased focus is being applied to developing truly secure methods for the protection, shipment, and handling of reticles. Specific problems include: . Inadequate protection provided by current stepper storage boxes . Shortcomings of shipping containers and sealing mechanisms . Over-reliance on direct manipulation in reticle handling practices