As IC device downscaling gets closer to the sub-10 nm critical dimensions, conventional deposition/litho/etch integration schemes and patterning processes, based on photolithography and etching, are facing their fundamental limits for device downscaling. Atomically controlled depositions at specific locations can boost advances or enable innovative fabrication schemes. Of several paths being explored for novel bottom-up nanopatterning, area-selective atomic layer deposition (ASD) and area-selective wet etch (ASE) are attracting increasing interest because of its ability to enable both continued dimensional scaling and accurate pattern placement for next-generation nanoelectronics. In this talk, an overview of potential applications of ASD and ASE in IC manufacturing is provided together with insights into the most relevant surface reaction mechanisms.
The native self-alignment of area-selective deposition (ASD) processes makes this technology a promising solution for precise pattern positioning in the EUV era. The key challenge for any ASD process is its defectivity associated with the deposition on the growth-inhibiting surface. Therefore, the ability to qualify an ASD process using the appropriate set of in-line metrology tools is crucial for up-scaling of the technology. In this work, we present a new concept of area-selective ALD TiO2 growth and use it as an example to show the potential of in-line OCD and XPS tools for evaluation of ASD processes. The proposed novel process is based on selective growth of TiO2 on top of SiO2/SiN in the presence of plasma halogenated amorphous carbon (a-C:H) acting as a growth-inhibiting layer. The exposure of a-C:H to CF4 or Cl2 plasma results in formation of a thin halogen-rich film suppressing nucleation of TiO2, while the latter is minimally affected on the plasma treated SiNx or SiO2 layers. The selectivity was assessed on both blanket films and 45 nm half-pitch a-C:H line patterns. The analysis of blanket a-C:H substrates showed that the plasma chlorination provides a substantially more efficient growth inhibition as compared to the fluorination. However, the ability of the CF4-plasma to etch the topmost surface of the a-C:H makes it more favorable for application on a-C:H patterns, surface of which is typically contaminated with residues from hard-mask or from the patterning plasma. Therefore, the pre-cleaning of the a-C:H line pattern surface with CF4-plasma is required to restore the growth blocking efficiency of the chlorinated a-C:H.
Nowadays, some of the important problems in microelectronics technological node scaling down are related to interconnect delay, dynamic power consumption and crosstalk. This compels introduction and integration of new materials with low dielectric permittivity (low-k materials) as insulator in interconnects. One of such materials under consideration for sub 10 nm technology node is a spin-coated organosilicate glass layer with ordered porosity (37-40%) and a k-value of 2.2 (OSG 2.2). High porosity leads to significant challenges during the integration and one of them is a material degradation during the plasma etching. The low-k samples have been etched in a CCP double frequency plasma chamber from TEL. Standard recipes developed for microporous materials with k<2.5 and based on mixture of C4F8 and CF4 with N2, O2 and Ar were found significantly damaging for high-porous ULK materials. The standard etch recipe was compared with oxygen free etch chemistries based on mixture CF4 with CH2F2 and Ar assuming that the presence of oxygen in the first recipe will have significant negative impact in high porous ULK materials. The film damage has been analyzed using FTIR spectroscopy and the k-value has been extracted by capacitance CV-measurements. There was indirectly shown that vacuum ultraviolet photons cause the main damage of low-k, whereas radicals and ions are not so harmful. Trench structures have been etched in low-k film and cross-SEM analysis with and without HF dipping has been performed to reveal patterning capability and visualize the sidewall damage and. The bottom roughness was analyzed by AFM.
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