An in-line inspection method for estimating defect resistances from the grayscale of voltage contrast in scanning electron microscope (SEM) images of manufactured patterns was developed. This method applies a circuit simulator to calculate the intensity of the secondary electrons according to an equivalent-circuit model considering the charge-up voltage on the patterns. To accurately estimate the resistance of defects formed in a device, first, the simulator was improved by considering the variation in defect resistance, which strongly depends on the differential voltage between the plug surfaces and the backside wafer. The defect resistances were obtained from the measured current-voltage (I-V) characteristics of the intentional defect on the standard calibration wafers, in which some incomplete-contact defects were systematically formed. Next, to consider the effect of the electronic characteristics of the pattern under the normal plugs on the grayscale, the I-V characteristics of the normal plugs were measured. The equivalent circuit of the simulator was improved by taking into account the measured I-V characteristics. The calibration curve for the manufactured patterns was calculated from the improved circuit simulator. Finally, the inspection method was applied to estimate the resistance of defects formed on an static random access memory (SRAM) pattern. The calculated calibration curve was used to estimate the defect resistance from the voltage contrast formed on the defects in the manufactured SRAM patterns. The accuracy of the estimation was about an order of magnitude.
As the design rule for semiconductor device shrinks, metrology for the critical dimension scanning electron microscope
(CD-SEM) is not only for measuring the dimension but also the shape, such as 2D contour of hot-spot pattern and OPC
calibration-pattern. Accuracy of the shape metrology is dependent on distortion of CD-SEM image. The distortion of
magnification in horizontal direction (i.e. x-direction) can be measured by pitch-calibration method, that measures pitch
of identical vertical line patterns while view-shifting the identical pitch in x-direction. However, the number of
measurement point could not be sufficient because this method requires long measurement time. Not only the horizontal
magnification but also vertical magnification (i.e. y-direction) and shear deformation (i.e. distortion of shape) are
necessary to keep highly accurate measurement.
In this paper we introduce the view-shift method for quick and accurate measurement of the image-distortion. From
using this method, both local distortion of magnification and shape can be measured in horizontal and vertical directions
at once. Firstly, two SEM-images of evaluation sample are taken. The sample should have a lot of unique features, e.g.
Textured-Silicon. View-shift about one ninth of the image size should be done by two images, and There are a lot of
unique features in overlapped region between two images. As distribution of the unique features, displacement between
two images indicates the local image-distortion. The dislocation of sample contour from distortion is estimated from the
local-distortion. The image-dislocation on a tool evaluated in this paper is less than 0.5 nm. It is a tolerated size for
current device process. However, it could be increased under the noisy external environment.
An in-line inspection method for estimating defect resistances from the grayscale of voltage contrast in SEM images
of manufactured patterns was developed. This method applies a circuit simulator to calculate the intensity of the
secondary electrons according to an equivalent-circuit model considering the charge-up voltage on the patterns. To
accurately estimate the resistance of defects formed in a device, first, the simulator was improved by taking the variation
of defect resistance into account, which strongly depends on the differential voltage between the plug surfaces and the
backside wafer. The defect resistances were obtained from the measured I-V characteristics of the deliberately formed
defect on the standard calibration wafers, in which some incomplete-contact defects were systematically formed. Next,
to consider the effect of the electronic characteristics of the pattern under the normal plugs on the grayscale, the I-V
characteristics of the normal plugs were measured. The equivalent circuit of the simulator was improved by taking into
account the measured I-V characteristics. The calibration curve for the inspected patterns was calculated from the
improved circuit simulator. Finally, the inspection method was applied to estimate the resistance of defects formed on
an SRAM pattern. The calculated calibration curve was used to accurately estimate the defect resistance (with an
accuracy of about an order of magnitude) from the voltage contrast formed on the defects in the inspected SRAM
patterns.
KEYWORDS: Resistance, Semiconducting wafers, Scanning electron microscopy, Calibration, Inspection, Silicon, Manufacturing, Transmission electron microscopy, Electron microscopes, Linear filtering
We develope an in-line inspection method for partial-electrical measurement of defect resistance, which is quantitatively estimated from the voltage contrast formed in a scanning electron microscopy (SEM) image of an incomplete-contact defect. We first manufacture standard calibration wafers for the voltage-contrast calibration. The contact resistance of systematically formed defects varied from 108 to 1017 . Then, we quantitatively analyze the gray scales of these defect images captured using a review SEM. As a result, calibration curves for estimating the contact resistance of the incomplete-contact defect are obtained at a probe current of 60 pA and a charging voltage of 4 V. The estimated contact resistance is between 107 and 1012 . Finally, this inspection method is applied to wafers manufactured for a static random access memory device. Accordingly, the gray scales of defective plugs formed for shared contact patterns are classified into two levels. The resistances of these defects are estimated from the calibration curve. The estimated resistances of the lower contrast defects (with an accuracy of about one order of magnitude) agree well with the resistances measured using a nanoprober. The resistances of the higher contrast defects are estimated as well, although they are too high to be measured using a nanoprober.
An in-line inspection method for partial-electrical measurement of defect resistance, which is
quantitatively estimated from the voltage contrast formed in an SEM image of an incomplete-contact
defect, was developed. This inspection method was applied to wafers manufactured for an SRAM
device. That is, the gray scales of the defect images captured on an SRAM plug pattern were
quantitatively analyzed. Accordingly, the gray scales of defective plugs formed for shared contact
patterns were classified as two levels. The higher contrasts, which were calculated from the grayscales
of the darker defects, were about 100%; the lower contrasts, which were calculated from the grayscales of
the other defects, were from 38% to 60%. The resistances of these defects were estimated from a
calibration curve obtained from the grayscales of the SEM images and the resistances of deliberately
formed failures on standard wafers for voltage-contrast estimation. The estimated resistances of the
lower-contrast defects (with an accuracy of about an order of magnitude) agree well with the resistances
measured by nano-prober. It is concluded that this in-line inspection method for partial-electrical
measurement is a useful technique for defect classification based on defect resistance and defect mode.
We analyzed the electron-irradiation damage induced by electron-beam inspection of metal nitride oxide semiconductor (MNOS) capacitors with various gate-dielectric thicknesses. Damage induced in an MNOS capacitor with a SiON dielectric for high-performance CMOS devices was compared to that induced on a metal oxide semiconductor (MOS) capacitor. We found that there is no remarkable difference between the damage to MOS capacitors and that to metal nitride oxide semiconductor MNOS capacitors. Damage was induced when a high-energy electron beam, whose electron range was larger than the thickness of the gate electrode, was irradiated. The induced damage strongly depends on the thickness of the gate dielectric. When the beam was irradiated onto a capacitor with a gate-dielectric thickness of 10.0 nm the flatband voltage shifted. When the beam was scanned onto a capacitor with a gate-dielectric thickness of 4.0 nm, the flatband voltage shifted minimally. However, the leakage-current density increased to 10−7 A/cm2 at a gate voltage of 3.0 V. On the other hand, when the beam was scanned onto an MNOS capacitor with 2.5-nm-thick dielectric, not even the leakage current was increased. Accordingly, for damage-free inspection when a gate-dielectric thickness is 4.0 nm or more, the beam energy needs to be lower so that the electron range is shorter than the thickness of the gate electrode.
We developed an in-line inspection method for partial-electrical measurement of contact resistance,
which is quantitatively estimated from the voltage contrast formed in an SEM image of an
incomplete-contact defect. At first, standard calibration wafers were manufactured for the voltage-contrast
calibration. The contact resistance of systematically formed defects was varied from 108 to 1017 ohms. We
quantitatively analyzed the grayscale of these defect images captured by a review SEM. Then, the
relationship between the grayscales of the defect images captured from these standard calibration wafers
and the contact resistances of the defects was studied. We obtained a uniform, stable grayscale of the
SEM images of each standard calibration wafer. As a result, calibration curves for estimating the contact
resistance of the incomplete-contact defect were obtained at a probe current condition of 80 pA and
charging voltages of 1 and 2 V. The estimated contact resistance under these inspection conditions was
between 1010 and 1016 ohms. Using this in-line inspection method, we demonstrated wafer mapping of
contact resistances calibrated from grayscales of defect patterns. We could not determine whether contact
resistances on a wafer widely varied unless we used this method.
We analyzed the electron-irradiation damage induced by electron-beam inspection of MNOS
capacitors with various gate-dielectric thicknesses. Damage induced in a MNOS capacitor with SiON
dielectric for high-performance CMOS devices was compared with that induced on a MOS capacitor with
SiO2 dielectric. We found that there is no remarkable difference between the damage to MOS capacitors
and that to MNOS capacitors. The induced damage strongly depends on the thickness of the gate
dielectric. Damages were induced when a higher-energy electron-beam, whose electron range was
larger than the thickness of the gate electrode, was irradiated. When the electron beam was irradiated to
a MOS capacitor with gate-dielectric thickness of 10.0 nm the flat-band-voltage shifted due to the created
traps. When the electron beam was scanned to a MOS or MNOS capacitor with gate-dielectric thickness
of 4.0 nm, Vfb shifted by less than 6 mV. However, the leakage-current density increased to 10-7 A/cm2
at gate-electrode voltage of 3.0 V. On the other hand, when the electron beam was scanned on a MNOS
capacitor with 2.5-nm-thick SiON dielectric, even the leakage current density was not increased.
Accordingly, for damage-free inspection when gate-dielectric thickness is 4.0 nm or more, the
electron-beam energy should be lower so that the electron range is smaller than the thickness of the gate
electrode.
We analyze the electron-irradiation damage induced in wafers by scanning electron microscope (SEM) inspection, which uses SEM images of voltage contrast formed by the charges on the pattern. The effects of electron-beam energy and charging on a metal-oxide semiconductor (MOS) capacitor are studied. We find that the higher energy electron beam, whose electron range is larger than the thickness of the gate electrode, creates traps at the interface between the silicon substrate and the gate dielectric. The flat-band voltage is shifted by the created traps. Although these traps are created by the transmission of the electron beam into the dielectric, they are not created only by charging on the gate electrode; neither is an oxide fixed charge created in the MOS capacitor. Accordingly, for damage-free inspection of MOS devices, the electron-beam energy should be low enough that the electron range is smaller than the thickness of the gate electrode. On the other hand, the flat-band voltage does not shift, owing to charging on the pattern surface during the electron irradiation. However, the gate dielectric is broken down by charging on the gate electrode at high voltage. Accordingly, for damage-free inspection, the charging voltage should be controlled so as not to break down the gate dielectric.
We analyzed the electron-irradiation damage induced in wafers by SEM inspection, which uses SEM images of voltage contrast formed by the charges on the pattern due to the electron irradiation. MOS capacitors were selected as samples because of their characteristic sensitivity. We studied the effects of electron-beam energy and charging on a MOS-capacitor test element group. To determine flat-band voltage, density of created traps, and oxide fixed charges in the MOS capacitors before and after the irradiations of the capacitors by electron beams under various conditions, we measured high-frequency and quasi-static capacitance-voltage characteristics. We found that the higher-energy electron beam, whose electron range was larger than the thickness of the gate electrode, created traps at the interface between the silicon substrate and the gate dielectric. The flat-band voltage of the MOS capacitor was shifted by the created traps. Although these traps were created by the transmission of the electron beam into the dielectric, they were not created only by charging on the gate electrode; neither was an oxide fixed charge created in the MOS capacitor. Accordingly, for damage-free inspection of MOS devices, the electron-beam energy should be low enough that the electron range is smaller than the thickness of the gate electrode. On the other hand, the flat-band voltage did not shift owing to charging on the pattern surface during the electron irradiation. However, the gate dielectric was broken down by charging on the gate electrode at high voltage. Accordingly, for damage-free inspection, the charging voltage should be controlled so as not to break down the gate dielectric.
KEYWORDS: Scanning electron microscopy, Electron microscopes, Spatial resolution, Electron beams, Semiconducting wafers, Monte Carlo methods, 3D metrology, Silicon, Metrology, Particles
We propose a technique using high-energy scanning electron microscope (SEM), which has the advantage of measuring 3-D structures and underlayer structures when compared to conventional low-energy SEM, to meet future metrology requirements. At first, we demonstrate that a technique using high-energy SEM has the advantages of measuring gate structures with a spatial resolution of a few nanometers. For example, a notched gate structure was most clearly visible when the beam energy is at 200 keV. Another example of a polyside gate with a sidewall spacer was most clearly visible at 100 keV. In addition, we studied the relationship between the thickness of the upper layer and beam energy at which the structure of the underlayers can be observed. The beam energy should be high enough to pass through the upper layer without the incident beam becoming broader, but low enough for the incident electrons to be backscattered at the structures in the underlayer. We could observe the line structures at a depth of 800 nm or less using an incident beam with energy from 50 to 100 keV.
KEYWORDS: Scanning electron microscopy, Electrons, Spatial resolution, Monte Carlo methods, 3D metrology, Control systems, Semiconducting wafers, Manufacturing, Metrology, Optical inspection
Manufacturing integrated devices with faster clock speeds requires the fine control of three-dimensional gate structures, including line-edge roughness, sidewall angles, and sidewall structures, as well as the control of line widths. In addition, a way to observe underlying structures in devices with multi-layer interconnects is required. As a way to meet future metrology requirements, we propose the use of high-energy scanning electron micrscopy (SEM), which is better suited to the measurement of 3-D structures and underlying structures than conventional low-energy SEM.
High-energy SEM is shown to reveal subsurface structures that are not detected by low-energy SEM. Firstly, a motched gate structure and a polycide gate with a sidewall spacer are observed with spatial resolutions of a few nanometers. The relationship between the thickness of the upper layer and beam energy at which underlying structures are observable is also investigated. The beam should be energetic enough to pass through the upper layer without being broadened, but weak enough that incident electrons are back-scattered by the underlying structures. We were able to observe line structures at depths of up to 800 nm by using incident beams with energy levels from 50 to 100 keV.
KEYWORDS: Inspection, Semiconducting wafers, Electron beams, Dry etching, Scanning electron microscopy, Selenium, Silicon, Signal detection, Etching, Linear filtering
We developed a technique using electron beams for inspecting contact holes immediately after dry etching and detecting incomplete contact failures. Wafers with deep-submicron contact holes that had high aspect ratios of 10 could be detected during practical inspection time by controlling the charging effect on the wafer surfaces. Measurements of the energy distribution in the secondary electrons exhausted from the bottom of the holes indicated that they were accelerated by the charge-up voltage on the wafer surfaces. Our analysis showed that high-density electron beams must be used to charge the surfaces when the aspect ratio is high. The minimum thickness of the residual SiO2 that could be detected at the bottom of the contact holes was 2 nm using an aspect ratio of 8. Applying this mechanism to optimize the dry etching process in semiconductor manufacturing showed that we could achieve reliable process control.
KEYWORDS: Inspection, Semiconducting wafers, Electron beams, Selenium, Signal detection, Dry etching, Scanning electron microscopy, Silicon, Semiconductor manufacturing, Process control
We developed a technique using electron beams for inspection contact holes immediately after dry etching and detecting incomplete contact failures. Wafers with deep-sub-micron contact \holes that had high-aspect-ratios of 10 could be detected during practical inspection time by controlling the charging effect on the wafer surfaces. Measurements of the energy distribution in the secondary electronics exhausted from the bottom of the holes indicated that they were accelerated by the charge up voltage on the wafer surfaces. Our analysis showed that high-density electron beams must be used to charge the surfaces when the aspect ratio is high. The minimum thickness of the residual SiO2 that could be detected at the bottom of the contact holes was 2 nm using an aspect ratio of 8. Applying this mechanism to optimize the dry etching process in semiconductor manufacturing showed that we could achieve reliable process control.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.