Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.
This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.
As the technology node shrinks, ArF Immersion reaches the limitation of wafer patterning, furthermore weak point during the mask processing is generated easily. In order to make strong patterning result, the design house conducts lithography rule checking (LRC). Despite LRC processing, we found the weak point at the verification stage of optical proximity correction (OPC). It is called the hot spot point (HSP). In order to fix the HSP, many studies have been performed. One of the most general hot spot fixing (HSF) methods is that the modification bias which consists of “Line-Resizing” and “Space-Resizing”. In addition to the general rule biasing method, resolution enhancement techniques (RET) which includes the inverse lithography technology (ILT) and model based assist feature (MBAF) have been adapted to remove the hot spot and to maximize the process window. If HSP is found during OPC verification stage, various HSF methods can be applied. However, HSF process added on regular OPC procedure makes OPC turn-around time (TAT) increased.
In this paper, we introduce a new HSF method that is able to make OPC TAT shorter than the common HSF method. The new HSF method consists of two concepts. The first one is that OPC target point is controlled to fix HSP. Here, the target point should be moved to optimum position at where the edge placement error (EPE) can be 0 at critical points. Many parameters such as a model accuracy or an OPC recipe become the cause of larger EPE. The second one includes controlling of model offset error through target point adjustment. Figure 1 shows the case EPE is not 0. It means that the simulation contour was not targeted well after OPC process. On the other hand, Figure 2 shows the target point is moved -2.5nm by using target point control function. As a result, simulation contour is matched to the original layout. This function can be powerfully adapted to OPC procedure of memory and logic devices.
DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory
and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore
device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature
(MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based
(MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall
RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm
complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One
example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified
experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only
on the very local geometric environment, which is important in applications where consistent signal propagation is of
MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide
variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF
placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows
for efficient investigations of future technology nodes as the number of interactions between local layout features
increases beyond what RBAF algorithms can effectively support
Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF
methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement
options might result in relatively improved process window compared to an independent approach since two methods
are capable of supplement each other with a complementary advantages.
In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and
manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a
conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to
Although technical issues remain to be resolved, EUV lithography is now a serious contender for critical
layer patterning of upcoming 2X node memory and 14nm Logic technologies in manufacturing. If
improvements continue in defectivity, throughput and resolution, then EUV lithography appears that it will
be the most extendable and the cost-effective manufacturing lithography solution for sub-78nm pitch
complex patterns. EUV lithography will be able to provide a significant relaxation in lithographic K1
factor (and a corresponding simplification of process complexity) vs. existing 193nm lithography. The
increased K1 factor will result in some complexity reduction for mask synthesis flow elements (including
illumination source shape optimization, design pre-processing, RET, OPC and OPC verification).
However, EUV does add well known additional complexities and issues to mask synthesis flows such as
across-lens shadowing variation, across reticle flare variation, new proximity effects to be modeled,
significant increase in pre-OPC and fracture file size, etc.
In this paper, we investigate the expected EUV-specific issues and new requirements for a production
tapeout mask synthesis flow. The production EUV issues and new requirements are in the categories of
additional physical effects to be corrected for; additional automation or flow steps needed; and increase in
file size at different parts in the flow. For example, OASIS file sizes after OPC of 250GigaBytes (GB) and
files sizes after mask data prep of greater than three TeraBytes (TB) are expected to be common. These
huge file sizes will place significant stress on post-processing methods, OPC verification, mask data
fracture, file read-in/read-out, data transfer between sites (e.g., to the maskshop), etc. With current methods
and procedures, it is clear that the hours/days needed to complete EUV mask synthesis mask data flows
would significantly increase if steps are not taken to make efficiency improvements. Therefore, we also
analyze different options for reducing or alleviating the EUV specific issues mentioned above and the
expected cost/benefit tradeoffs associated with these options. The options include understanding the
accuracy vs. run-time benefit of different rule-based and model-based approaches for several correction
issues; predicting the implications and improvements expected with different flow automation options; and
estimating possible productivity improvements with different flow parallelization choices and upcoming
multi-core processors. Optimal combinations of options and accuracy/effort/runtime results can be seen to
enable EUV lithography tapeout flows to achieve equal or better total time when compared to current
193nm optical lithography tapeout flow times.
In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.
Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask
proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include
the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict
the entire lithography process correctly even using advanced optical and resist models. In order to compensate
for the mask proximity effect within OPC a special model is required along with changes to the OPC flow.
This article presents a method for producing such a model and OPC flow and shows the difference in results
when they are used.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
Deep-UV (DUV) lithography has been developed to define minimum feature sizes of sub-100 nm dimensions of devices
semiconductor. In response to this trend, DUV mask technology has been proposed as an effective technique for
considering the reduction of mask making cost, especially, in low volume designs. However, the requirement of tight CD
control of the mask features in advanced devices is resulted in increasing of mask cost. In this research, we discussed
two different typed image tones comparison, positive and negative tone, in DUV lithography. The choice of final mask
tone needs to be selected as function of pattern density and shape. The evaluation items to judge if the mask is good are
the OPC model accuracy, resolution and mask throughput. Both mask process and manufacturing throughput are affected
by image tone type of positive and negative. This paper will show the procedures and results of experiment.
It is becoming difficult to achieve stable device functionality and yield due to the continuous reduction of layout dimensions. Lithographers must guarantee pattern fidelity throughout the entire range of nominal process variation and diverse layout.
Even though we use general OPC method using single model and recipe, we usually expect to obtain good OPC results and ensure the process margin between different devices in the sub-100nm technology node.
OPC Model usually predicts the distortion or behavior of layout through the simulation in the range of measured data. If the layout is out of range from the measured data, or CD difference occurred from the topology issue, we can not improve the OPC accuracy with a single OPC model.
In addition, as the design rule has decreased, it is extremely hard to obtain the efficient OPC result only with a single OPC recipe. We can not extract the optimized single OPC recipe which can cover all the various device and layout. Therefore, we can improve the OPC accuracy and reduce the turn around time related to the OPC operation and mask manufacturing in sub-100nm technology node by applying the optimized multi OPC recipes to the device which contains the various patterns like SoC.
Optical Proximity Correction (OPC) often reaches its limitation, especially low-k imaging. It results in yield drop by bridging, pinching, and other process window sensitive issues. It happens more when the original layout contains OPC-unfriendly patterns. With OPC-unfriendly layout, OPC model generates totally unexpected results such as narrow space, small jog, small serif and etc. Those unexpected OPC results induce bridged patterns as well as narrow process margin. And they will give direct yield loss of device.
Thus, it is critical to implement the flow for Litho Friendly Design (LFD) and nevertheless simulation-based OPC verification. In this study, a new approach of OPC has been tested, which contains the simulation based analysis of OPC failure and in turn out reconstruct OPC features in a way to fix not only bridging and pinching but also to improve process window. This proves to reduce mask respin by 50% or more. It also has been tried to be a complementary checking in addition to conventional CD monitor in pilot production.