CMOS imaging has experienced significant developement in the last decades. At the center of this progress lies the pixel, composed of a light sensitive area (photodiode) coupled to a network of transistors. As the pixels sizes shrink, the light sensitive area gets smaller and requires light focusing assistance. To address this issue, microlenses are added to the top of the pixels stack. The microlenses are made of polymer resist transparent to the wavelength of interest. Creating such structures is not straightforward and requires complex process steps, especially when arrays of multiple shapes and sizes are needed. The grayscale approach appears as a promising alternative since this unconventional lithography method can produce variable shapes and sizes in a single lithography step. Mask data preparation is the most critical step for grayscale lithography. A widespread strategy is to experimentally establish the relationship between a given dose (corresponding to a specific chromium density on the mask) and the remaining resist thickness after development. The relationship, also known as contrast curve, is used as a transfer function to compute a suitable mask for the given resist. Our approach is to create a simplified grayscale model able to predict the resist response under any given mask and illumination condition. Using the classic contrast curve approach we have designed a mask composed of sub 5μm patterns and evaluated the resist profile prediction of the contrast curve approach compared to our grayscale model on various patterns including microlenses, pyramids and bowl shapes. Reults show that the contrast curve approach is no longer appropriate when the dimensions reduce below 5μm.
The advance in microlithography has greatly helped the development of micro optical elements. Large array of microlenses can now be fabricated in the same fashion as manufacturing of integrated circuit at low cost and high yield [1-2].
Because microlens array requires well-defined and continuous surface relief profile, special methods are needed to supplement the normal microlithography to produce those spherical structures . Various techniques have been developed, and the most widely used is multi-step photolithography with thermal resist reflow. However, the alternative grayscale photolithography technique appears to be the one as the most flexible and versatile method .
Indeed, this approach is a one-level lithography process enabling the development of 3D profiles in a photoresist masking layer. In addition, with the need to maintain or improve image quality at an ever-smaller pixel size, grayscale technic can offer one way to compensate the loss of the photosensitive area by achieving zero-gap microlens. One other advantage of grayscale is the possibility to have, from a single lithography, objects of different shapes, but also at the same time of different sizes (especially heights); which is possible with classical lithography only by doing multi-patterning.
There are several options for performing grayscale lithography, for example the HEBS mask (high energy beam sensitive) which darkens under exposure to electrons. The option that has been chosen is to use a grayscale reticle, with varying chromium features densities that locally modulate the intensity of transmitted UV light. Being non-uniformly exposed, this allows the creation of a relief structure in the resist layer after development. The resist height after development depends on the intensity of the incident light, the exposure time and the contrast of the resist. So contrary to conventional lithography where the goal is to achieve straight resist pattern profiles, grayscale lithography enables the realization of progressive profiles, which requires smooth resist contrast curve. The other specificity of these resists is that they must crosslink without flowing.
In this paper, we evaluate resists from different suppliers to generate microlenses smaller than 5μm via a grayscale mask. The study consists in establishing the contrast curves of these resists according to different process parameters, giving the designer great control of grayscale levels that can be achieved for a given resist. Then, pattern various microlenses shapes in these resists to evaluate the residual resist thickness according to the gray levels. With the final objective of establishing a relationship between these contrast curves and the profile variations at the microlens level to compute a suitable and accurate grayscale mask .
There has been a significant increase of optical applications in the last decade, either embedded into complex multifunction devices such as smartphones, or for imaging purpose as cameras. Core of such optical systems are microlens arrays, used for light gathering or light emitting. The most commonly used manufacturing method by the industry is the thermal reflow of photoresist polymer. The method consists in melting previously patterned photoresist dots in order to form the lenses. But the resist shaping into a microlens is not as straight forward, since the final microlens needs to match shaping criteria to maximize the device optical efficiency. The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps. This would help designers and lithographer to evaluate beforehand the final shape of a certain design at the end of the process flow. It would then offer the possibility to identify from the start the correct design to embed onto the photomask guaranteeing the fabrication of the desired microlens. A 3D compatible and computation efficient reflow simulation software is proposed in this paper, in line with a Design Process Technology Co-optimization (DTCO) approach. It allows the fast 3D reflow simulations of hundreds of different resist patterns, taking as input a CAD design and returning the corresponding 3D microlens that will be formed. The purpose of this paper is to present the developed reflow modeling software solution and its calibration methodology. The use of the proposed alternative simulation flow for microlens optimization in a Resolution Enhancement Technics (RET) environment will also be described.
Directed Self Assembly (DSA) of block-copolymers (BCPs) is considered as a cost-effective solution to extend the performances of conventional lithography. In this work, we propose a smart surface modification technique to precisely control the surface affinity of guiding template used in the DSA graphoepitaxy process flows. The presented method consists in the UV irradiation of copolymers brushes in order to locally tune their surface affinity. By this way, we are able to differentiate the surface affinities of guide sidewalls (PMMA-attractive) and guide bottom (non-preferential affinity). A complete DSA-module is demonstrated and implemented on a 300mm integration flow dedicated to the creation of silicon nanowires-like transistor.
In this paper we report on advances in DUV dry photolithography both for etching and implantation of silicon photonic devices. We explain why silicon patterning is a critical building block in silicon photonics and what are the challenges related to that process. Furthermore, it also occurs that some silicon photonic devices need implantation lithographic conditions which are also specific to the technology. For that purpose, we developed a dedicated DUV 193nm implantation lithography to address that need.
We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.