As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.
A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic
process technologies. A noble technology combined a number of potential confliction of DFM techniques into a
comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon
diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are
optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and
advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve
manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented
in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5%
improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the
positive effect of the DFM techniques.
Proc. SPIE. 8327, Design for Manufacturability through Design-Process Integration VI
KEYWORDS: Photovoltaics, Metals, Image processing, 3D modeling, Scanning electron microscopy, Design for manufacturing, Optical proximity correction, Semiconducting wafers, Process modeling, Chemical mechanical planarization
As a result, low fidelity patterns due to process variations can be detected and eventually corrected by designers as early
in the tape out flow as right after design rule checking (DRC); a step no longer capable to totally account for process
constraints anymore. This flow has proven to provide a more adequate level of accuracy when correlating systematic
defects as seen on wafer with those identified through LFD simulations. However, at the 32nm and below, still distorted
patterns caused by process variation are unavoidable. And, given the current state of the defect inspection metrology
tools, these pattern failures are becoming more challenging to detect. In the framework of this paper, a methodology of
advanced process window simulations with awareness of chip topology is presented. This method identifies the expected
focal range different areas within a design would encounter due to different topology.
As patterning for advanced processes becomes more challenging, designs must become more process-aware. The
conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of
runtime for designers, and also requires the release of highly confidential process information. Therefore, a more
practical approach is required to make the In-Design process-aware methodology more affordable in terms of
maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair
(PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information.
Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very
easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical
Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and
released to check and fix subsequent designs.
This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created
from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process
hotspots in a design, specifically through the use of pattern matching and routing repair.
Traditionally model based CMP check and hotspot detection are only done at the top level of the design because full
chip assembly is required to capture CMP long range effect. When manufacturing hotspots are found just before tape out
and layout modification is required, this can disrupt the overall schedule by repeating the verification steps with the
changed layout. Hence getting feedback at early design stage is critical to ensure that the design is correct by
construction. In this paper, we present a model-based CMP-DFM methodology which is used at early design phases to
avoid CMP related manufacturing failures. An accurate CMP model has been developed and used to predict surface
topographies for 32nm designs as well as physical hotspots caused by dishing, erosion, and depth of focus. We
demonstrate how to apply a characterized 32nm CMP physical model to run block level simulation with little or no
context information. The block level simulation methodology allows designers to check block robustness against any
possible surrounding environments in which the block may be placed. This approach can be taken for corner case
analysis in CMP-aware RC extraction.
Automatic layout optimization is becoming an important component of the DfM work flow, as the number of
recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly
difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM
improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer
optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics,
while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained
intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base
Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements
(CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler
was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM
checking and by wafer yields.