Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX
KEYWORDS: Semiconducting wafers, Data modeling, Metrology, Defect detection, High volume manufacturing, Deep ultraviolet, Inspection, Detection and tracking algorithms, Process control, Etching, Optical lithography, Scanning electron microscopy, Sensors, Lithography, Scanners
As process window margins for cutting edge DUV lithography continue to shrink, the impact of systematic patterning defects on final yield increases. Finding process window limiting hot spot patterns and monitoring them in high volume manufacturing (HVM) is increasingly challenging with conventional methods, as the size of critical defects can be below the resolution of traditional HVM inspection tools. We utilize a previously presented computational method of finding hot spot patterns by full chip simulation and use this to guide high resolution review tools by predicting the state of the hot spots on all fields of production wafers. In experiments with a 10nm node Metal LELELE vehicle we show a 60% capture rate of after-etch defects down to 3nm in size, at specific hot spot locations. By using the lithographic focus and dose correction knobs we can reduce the number of patterning defects for this test case by ~60%.
The optimization of the source topology and mask design [1,2] is vital to future advanced ArF technology node development. In this study, we report the comparison of an iterative optimization method versus a newly developed simultaneous source-mask optimization approach. In the iterative method, the source is first optimized based on normalized image log slopes (NILS), taking into account the ASML scanner's diffractive optical element (DOE) manufacturability constraints. Assist features (AFs) are placed under the optimized source, and then optical proximity correction (OPC) is performed using the already placed AFs, in the last step the source is re-optimized using the OPC-ed layout with the AFs. The source is then optimized using the layout from the previous stage based on a set of user specified cost function. The new approach first co-optimizes a pixelated freeform source and a continuous transmission gray tone mask based on edge placement error (EPE) based cost function. ASML scanner specific constraints are applied to the optimized source, to match ASML's current and future illuminator capabilities. Next, AF "seeds" are identified from the optimized gray tone mask, which are subsequently co-optimized with the main features to meet the process window and mask error factor requirement. The results show that the new method offers significant process window improvement.
Optical proximity correction (OPC) procedure for modifying designs requires an OPC setting effectively accounting for manufacturing and imaging constraints. Reticle-writing and imaging tool capabilities drive the choice for the minimum feature of an OPC model.
Aggressiveness of an optical proximity correction is determined by a discretization setting for an OPC algorithm. Some OPC scheme parameters are there to restrict the minimum spacing and width to avoid circuit failures. The OPC minimum spacing parameter controls bridging lines. The OPC minimum width parameter limits the correction of trenches responsible for circuit breakdown. An aggressive choice of minimum spacing and width for an OPC setting can results in circuit failure: shortage or breakdown. The conservative approach results in poor circuit performance.
The methodology was deployed at LSI Logic Corporation for empirical optimization of the OPC minimum spacing/width settings for a no failure imaging solution of OPCed masks. The proposed procedure is particularly beneficial for dark field metal interconnect masks. The approach was successfully validated for 130nm and 90nm backend technology metal layers.
A methodology and a Monte Carlo simulation flow with integrated LSI Logic's OPC package, Molotof, was applied to the 65nm poly line sensitivity analysis. Strong phase shift mask (sPSM) manufacturing specifications were optimized to obtain image critical dimensions (CD) and image placement errors (IPE) complying with technology design rules. Reticle manufacturing statistical errors of phase depth, phase width, and phase intensity imbalance were used to generate a virtual sPSM for imaging poly lines. A criterion for qualifying reticle specification is to obtain all latent image CDs and IPEs within a design rule allowed range for a given mask specification. The approach allows for computing reticle and litho budgets into CD imaging performance. We present simulation and empirical results of statistical analysis of the 65nm poly line (clear field) printability, and a method for optimizing a strong phase shift reticle specification. Sensitivity to a single parameter variation and full statistical analysis of the 65nm poly line imaging performance affected by manufacturing errors is presented. The optimum reticle specification, yielded 100% of critical dimensions and image placement errors, was found in simulation and confirmed by empirical data.
A methodology has been developed to measure OPC model robustness as a function of systematic and statistical process variations. The analysis includes comparison of imaging solutions with several different OPC models generated for different writing tools and lithography process conditions. This approach allows for definition of OPC model tolerance in the continually changing R&D and production environment. The question of when it is absolutely necessary to regenerate OPC models and when application of "the old" OPC model is acceptable is answered
This method has been applied at LSI Logic for qualifying a single OPC model for e-beam and laser reticle writing tools in back-end processes for the 0.13um technology node. The OPC model tolerance qualification takes additional time and engineering effort, but it provides pay back through comparable or better product performance and lower costs.
Production readiness of phase-edge/chromeless reticles employing off-axis illuminations for 65nm node lithography is assessed through evaluation of mask design conversion and critical layer lithography performance. Using ASML /1100ArF scanners, we achieved k1=0.33 for chromeless phase shift mask (crlPSM) with more than 0.6um DOF for dense features. Subresolution assist features allow for acceptable depth of focus through pitch. However, chromeless feature linearity fall-off continues to be a major issue hampering the acceptance of crlPSM for production. Several mask data conversion schemes such as chromeless gratings and chrome patches have been proposed as viable solutions to mitigate the chromeless linearity fall-off issue. We evaluated chromeless gratings, chromeless rims and chrome patches and report on their performance in resolving the chromeless linearity fall-off issues as well as mask process complexity associated with each solution.
The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.
Maskless lithography imaging based on SLM tilt mirror architecture requires illumination of light on a non-planar reflective topography. While the actual mirror dimensions can be much larger than the wavelength of light, the spacing between mirrors and the tilt range of interest are on the order of the wavelength. Thus, rigorous electromagnetic solution is required to capture light scattering effects due to the non-planar topography. We combine high NA imaging simulation with rigorous simulation of light scattering from the mirrors to study its effects on 65nm maskless lithography imaging. We vary mirror size, mirror tilt arrangemetn, feature type and illumination settings and compare the rigorous light scattering imagign resutls wtih standard imaging simulations using Kirchoff approximation. While electromagnetic scattering effects are present in the form of lateral standing waves and edge streamers in reflected light near-field intensity, they have negligible effects on SLM imaging for mirror sizes more than 1μm2. The effects of mirror tilt arrangement on diffraction orders aer used to study the through-focus behavior of alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement are confirmed and a multipass overlay scheme giving further image fidelity improvements is suggested.
Manufacturability and economical viability of etched quartz solutions for 65nm node critical layer lithography is assessed through evaluation of mask technology conversion complexity, mask process complexity, wafer processing cost and SRAM cell critical layer lithography performance. The etched quartz technologies under consideration are the full-layout alternating phase shift mask solution (FullPhase altPSM) and chromeless hard shifter phase shift mask solution (crlPSM). Using 0.63 NA exposures, we achieve k1 =0.29 (DOF=0.6um) and k1 =0.33 (DOF=0.8um) for altPSM and crlPSM, respectively. 60nm isolated feature DOF is more than 0.8um for altPSM. The crlPSM isolated feature DOF without sub resolution
assist features is about 0.3um. Simulations results of crlPSM isolated features with sub resolution assist features using NA=0.75 show that DOF of 0.3um is attainable for crlPSM. Experimental results are used to calibrate wafer volume cross over model for these competing technologies with specific focus on die size, k1 and DOF related yield as wafer processing cost drivers. Results show that altPSM has lower wafer processing cost due to better lithography yield at smaller die sizes. Thus, though the mask set of altPSM solution is more expensive than crlPSM, the altPSM solution is more economical for high volume production of 65nm node technologies. The wafer volume crossover model allows for the most cost effective mask solution to be employed for a given logic device and wafer volume expectation.
The challenge of delivering acceptable semiconductor products to customers in timely fashion becomes more difficult as design complexity increases. The requirements of current generation designs tax OPC engineers greater than ever before since the readiness of high-quality OPC models can delay new process qualifications or lead to respins, which add to the upward-spiraling costs of new reticle sets, extend time-to-market, and disappoint customers. In their efforts to extend the printability of new designs, OPC engineers generally focus on the data-to-wafer path, ignoring data-to-mask effects almost entirely. However, it is unknown whether reticle makers' disparate processes truly yield comparable reticles, even with identical tools. This approach raises the question of whether a single OPC model is applicable to all reticle vendors. LSI Logic has developed a methodology for quantifying vendor-to-vendor reticle manufacturing differences and adapting OPC models for use at several reticle vendors. This approach allows LSI Logic to easily adapt existing OPC models for use with several reticle vendors and obviates the generation of unnecessary models, allowing OPC engineers to focus their efforts on the most critical layers.
A number of techniques are used for resolution enhancement in leading edge lithography. As feature dimensions shrink, these resolution enhancement techniques (RETs) become more aggressive, causing huge increases in data volume, complexity and write time. The results of these techniques are verified using methods such as SEM measurements of resist or etched structures on the wafer. These RETs tend to either over or under-compensate by way of the suggested corrections or enhancements with respect to the actual device operation. In addition, the systematic and random metrology errors inherent in wafer level top-down SEM measurements become more significant as feature sizes shrink and tolerances become tighter. These errors further cloud the decision as to which RET is most suitable and necessary. To overcome these problems, we have designed an electrical test vehicle which targets those geometries most prevalent in the cells for a given technology. Electrical test (E-test) structures are then varied around these geometries covering the design rule space. Device parameters are measured over this design space for various RETs. This method reconciles the accuracy or effectiveness of RET models using electrical device parameters and uses the same to choose the RET which results in the lowest NRE while at the same time meeting all electrical requirements.
Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.
ASIC companies face consistent pressure to reduce cost, improve quality, and decrease the time to production for reticles used in integrated circuit fabrication. In order to meet these objectives, the Reticle Engineering group at LSI Logic has developed an efficient and accurate defect control methodology. Three case studies in this paper highlight a unique defect management strategy. The scenarios describe rejecting a reticle to the vendor, releasing a reticle to the fab while deeming a defect innocuous, and tracking a reticle through production with a known yield impacting defect. The defect management solutions highlighted in this paper include a web based defect classification and disposition system to supplement the Lasertec MD2000 die to die inspection tool, virtual inking of affected die, and a production process flow for defect verification on silicon wafer prints. Quantitative results are shown, illustrating the elimination of vendor induced repeaters, improvements in baseline defect density, and improved cycle time for defect analysis and inspection flows.
`Non-critical' levels such as implant layer consume a large volume of photoresist. This work was done to choose a cost- effective, high performance implant resist implant resist. IN addition to resolution considerations, outgassing during implant, speed and cost were all evaluated to choose the successful candidate. Through this effort a new resist formulation, SumiresistTM PFM-10 was compared with other existing I-line formulations.