3-dimensional chiplet device architectures are expected to provide improved device performance, efficiency, and footprint beyond what is capable with 2-dimensional scaling technologies. Thick resist lithography of damascene and plating resists, as well as organic dielectric materials, plays a critical role in chiplet integration. However, thick resist lithography requires viscous resist solutions, specialized tooling, and long processing times. This makes patterning using these resists inherently prone to uniformity issues, which has become a crucial issue for scaling. This work highlights two strategic areas of thick resist patterning development: improved resist coating methods; and enhanced focus control during exposure. Herein, we show a track-based method for carefully controlled uniformity of the resist coating thickness, with some sacrifice of through-put. In addition, we show stepper-based focus methods to account for die level variations in resist and wafer thickness, as well as local topography. Combined, these provide precise cross-wafer control of thick resist dimensions.
Extreme ultraviolet lithography (EUVL) has overcome significant challenges to become an essential enabler to the logic and memory scaling roadmap. Despite its significant progress, resist photo speed, and defectivity remains the main concerns for high-volume manufacturing. To overcome these issues, high-performance EUV resist processes are needed. The high-performance resist process must simultaneously meet multiple requirements, such as a high resolution, high sensitivity, low roughness, low defect level, and good global CD uniformity (CDU). One of the high-performance resist candidates for future EUV scaling, and high NA EUV is Metal Oxide Resist (MOR). In our work, we introduce the new coater/developer hardware and new resist development techniques to improve photo speed, defectivity, and CDU without degradation of roughness in MOR. We will show that the new development methods significantly improve EUV dose to size (DtS) and micro-bridge (MB) while maintaining resist roughness performance post litho and post-etch. The new coater/developer hardware and processes are evaluated through a robust characterization methodology that includes an understanding of the defect modes at ADI (after development inspection) and AEI (after etch inspection), as well its ultimate correlation to electrical yield.
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