Dr. Nicolas Possémé Profile

Dr. Nicolas Possémé

at CEA-LETI

SPIE Involvement:

Author

Proceedings Article | 30 April 2023 Poster

Hierarchical patterning: sub-10 µm 3D structures nano-textured by block copolymer self-assembly

Raphaël Feougier, Maxime Argoud, Nicolas Posseme, Raluca Tiron

Proceedings Volume PC12497, PC124970N (2023) https://doi.org/10.1117/12.2654150

KEYWORDS: Microlens, Nanolithography, Silicon, Silica, Nanostructures, Microlens array, Lithography, Integrated modeling, HF etching, 3D modeling

Read Abstract +

Proceedings Article | 27 April 2023 Presentation + Paper

High spatial frequency on-device overlay characterization using CD-SEM contours

Thibaut Bourguignon, Bertrand Le Gratiet, Jonathan Pradelles, Sébastien Bérard-Bergery, Charles Valade, Nivea Schuch, Nicolas Possémé

Proceedings Volume 12496, 124960J (2023) https://doi.org/10.1117/12.2657914

KEYWORDS: Scanning electron microscopy, Overlay metrology, Data modeling, Optical testing, Metrology, Contour extraction, Lithography, Design and modelling

Read Abstract +

The on-device and target-less overlay (OVL) measurement adds various challenges to the conventional target-based one.¹ Most of the common solutions are based on the use of high voltage SEM to have a high resolution and see-through capabilities to see both layers entirely. To ensure repeatability and robustness the measurement is also generally realized on dedicated targets.^2–4 Another approach is explored in this work : it consists of a direct measurement on the device itself, without any dedicated target and using a CD-SEM that do not have see-through capabilities. To avoid any damage on the final device and to ensure a partial vision of the bottom layer, the measurement is realized post etch. What can a true on-device, target-less, SEM overlay metrology reveal of the process? To answer this question, a custom design-based on-device CD-SEM overlay metrology was developed.⁵ It allows measuring the overlay on any bilayer 2D structure, even partially hidden, provided that sufficient edges are visible. Thanks to this post-processing capacity to measure on partially hidden patterns, the CD-SEMs from the current tool park can be used and non-transparent layers can be investigated. After demonstrating the capability of the previously mentioned solution on synthetic SEM images,⁶ by taking advantage of the versatility of the method and of an improved bilayer contour extraction algorithm, one product wafer was measured densely at different steps of the process on several patterns. These extensive measurements aim to reveal overlay signatures at different spatial frequencies: intra-field, intra-chip and even inside a random logic array. This paper details and interprets the observed overlay measurement with models while investigating the matching between the different measurement patterns and the mismatches with the optical overlay. To conclude, the contour-based metrology offers the capability to extract highly valuable information from CD-SEM images and represents a great opportunity for on-device overlay measurement. By measuring directly the products’ patterns, the developed metrology shows a mismatch between optical and SEM measurements up to a couple of nanometers. A hybrid model, mixing SEM and optical measurements reduced by 15% the on-product residuals. Additionally, the local overlay variability could be evaluated and low amplitude chip signatures have been observed. This new information will help process engineers to improve the process characterization, leading to a better process control that results in an improved reliability.

Proceedings Article | 1 November 2022 Paper

Contour based on-device overlay metrology assessment using synthetic SEM images

Thibaut Bourguignon, Bertrand Le Gratiet, Jonathan Pradelles, Sébastien Bérard-Bergery, Guido Rademaker, Nicolas Possémé

Proceedings Volume 12472, 124720C (2022) https://doi.org/10.1117/12.2640140

KEYWORDS: Overlay metrology, Scanning electron microscopy, Monte Carlo methods, Metrology, Image processing, Image quality, Semiconducting wafers, Reliability

Read Abstract +

The shift of semiconductor industry applications into demanding markets as spatial and automotive led to high quality requirements to guaranty good performances and reliability in harsh environments. As reliability is directly related to a well-controlled process, characterizing the local overlay and its variations inside the chip itself becomes a real asset. While most available in-chip overlay metrologies require dedicated target or dedicated tools, we developed a new method that aims to augment the current SEM tool park into measuring the local overlay directly on the product. In a previous proceeding, this on-device and target-free overlay measurement based on CD-SEM contours has been assessed on SRAM patterns and showed promising results. The work presented here pushes forward this assessment using SEM synthetic images generated from the open-source Nebula simulator of electron-matter interaction. From a layout, a 3D geometry of the measured pattern can be generated, with materials and interfaces carefully defined. Then, a GPU-accelerated Monte-Carlo model simulates in tens of seconds the SEM image. This fast generation of images enables the use of synthetic SEM images in a digital twin system: they can be used to characterize and to challenge the overlay metrology, before applying it to real products. Indeed, a known overlay can be programmed in these images. This way the performances of the measurement algorithm can be assessed with a ground truth reference. Firstly, imaging parameters such as pixel size and noise have been varied in a wide range. This demonstrated a good accuracy and precision inside a defined measurement window with a coefficient of correlation above 0.996 and an offset lower than 0.2nm. In a second part, the influence of the pattern measured has been investigated and experimental results on SRAM could be reproduced using synthetic images. The origin of the loss of sensitivity has been identified and improvements in the contour extractions and used template led to a correlation with a slope of 1.03, an offset of 0.1nm and a Root Mean Square Deviation of 1.36 nm. Finally, the developed digital twin already showed behaviors in the measurement that were hidden in the on-wafer experiments, that helped assessing the method and which will be used in the future to define guidelines for template-based SEM-OVL measurements.

Proceedings Article | 26 May 2022 Presentation + Paper

Enabling on-device and target-free overlay measurement from CD-SEM contours

Thibaut Bourguignon, Régis Bouyssou, Jonathan Pradelles, Sébastien Bérard-Bergery, Bertrand Le-Gratiet, Romain Bange, Nivea Schuch, Thiago Figueiro, Nicolas Possémé

Proceedings Volume 12053, 120530C (2022) https://doi.org/10.1117/12.2613327

KEYWORDS: Overlay metrology, Scanning electron microscopy, Metrology, Image processing, Algorithm development, Feature extraction, Semiconducting wafers

Read Abstract +

Overlay is a critical parameter for any semi-conductor foundry, with a direct impact on the fabrication yield, on the quality, and on the performances of the product. Being able to full the overlay constraints has also a direct in influence on the capacity to scale down and to integrate vertically. In addition, the shift of semiconductor applications into more demanding markets such as spatial and automotive leads to higher specifications for the process control. In the semiconductor manufacturing, the overlay is usually measured optically using dedicated targets in the scribe lines. However, targets differ from the product by their dimensions of an order of magnitude larger and by their position up to a few millimeters far from it. This can lead to residual errors and mismatches in the correction sent to the scanner, thus lowering the fabrication yield and the global product quality. For years, many SEM in-device overlay techniques have been published, however they are generally related to new generation of SEM imaging and metrology equipment and require a new dedicated target. In our case, the ambition is to extend the usage of our current CD-SEM tool park. To do so, an on-device and target-free overlay measurement process has been developed. It is based on sub-pixel contour extractions from CD-SEM images and on the use of the design. From a single image, contours of the two layers of interest are extracted from the SEM image and a custom algorithm calculates the overlay as a difference of the realigned design centroids. This dedicated algorithm allows extracting various overlay measurements from one image and enables a production friendly implementation. To evaluate the performances of this method, it has been applied on the patterns of a SRAM with scanner-programmed overlay. The measurements are compared to the conventional optical measurements. On a basis of thousands on-device measurements, the developed method showed a promising 95% rate of successful measurements. Good correlation between the optical model and the CD-SEM measured overlay on the SRAM has been demonstrated, reaching a coefficient of correlation of 0.99 on a pattern where conventional centroid or CD based overlay are limited. Finally, the flexibility of the method to measure various patterns with an ease of recipe creation is shown. Contour-based metrology offers the capability to extract highly valuable information from SEM images while keeping the layers differentiation. The proposed measurement process, being automated and requiring relatively low human inputs is a promising solution for a SEM on device overlay metrology suitable in a high-volume manufacturing environment.

Proceedings Article | 22 February 2021 Presentation

Selective patterning using deposition and etch: case of area selective deposition

christophe vallee, Marceline Bonvalot, Taguhi Yeghoyan, Moustapha Jaffal, Nicolas Posseme, Remy Gassilloud, Thierry Chevolleau

Proceedings Volume 11615, 116150C (2021) https://doi.org/10.1117/12.2582079

KEYWORDS: Etching, Optical lithography, Deposition processes, Atomic layer deposition, Reactive ion etching, Plasma etching, Roads, Anisotropic etching, Wet etching, Transistors

Read Abstract +

Proceedings Article | 19 March 2018 Paper

Precise control of template affinity achieved by UV-assisted graphoepitaxy approach on silicon nanowires applications

P. Pimenta-Barros, G. Claveau, M. Argoud, Z. Chalupa, N. Allouti, C. Comboroure, G. Chamiot-Maitral, N. Posseme, L. Pain, R. Tiron, C. Navarro, C. Nicolet, I. Cayrefourcq

Proceedings Volume 10584, 105840C (2018) https://doi.org/10.1117/12.2297407

KEYWORDS: Etching, Silicon, Ultraviolet radiation, Directed self assembly, Polymethylmethacrylate, Scanning electron microscopy, Plasma, Nanowires, Line width roughness, Surface properties

Read Abstract +

Proceedings Article | 27 April 2017 Presentation

New 3D structuring process for non-integrated circuit related technologies (Conference Presentation)

Lamia Nouri, Nicolas Possémé, Stéfan Landis, Frédéric Milesi, Frédéric-Xavier Gaillard

Proceedings Volume 10144, 101440C (2017) https://doi.org/10.1117/12.2258603

KEYWORDS: Ions, Wet etching, Electron beam lithography, Silicon, Ion implantation, Lithography, Ion beam lithography, FT-IR spectroscopy, Microelectronics, Integrated circuits

Read Abstract +

Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration’s requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures.

In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one.

In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that “infinite” selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results.

The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.

Proceedings Article | 10 April 2017 Presentation + Paper

Nanoimprint, DSA, and multi-beam lithography: patterning technologies with new integration challenges

S. Landis, H. Teyssedre, G. Claveau, I. Servin, F. Delachat, M. L. Pourteau, A. Gharbi, P. Pimenta Barros, R. Tiron, L. Nouri, N. Possemé, M. May, P. Brianceau, S. Barnola, Y. Blancquaert, J. Pradelles, P. Essomba, A. Bernadac, B. Dal'zotto, S. Bos, M. Argoud, G. Chamiot-Maitral, A. Sarrazin, C. Tallaron, C. Lapeyre, L. Pain

Proceedings Volume 10149, 101490K (2017) https://doi.org/10.1117/12.2259966

KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing

Read Abstract +

SPIE Journal Paper | 25 August 2016

Surface affinity role in graphoepitaxy of lamellar block copolymers

Guillaume Claveau, Patrick Quemere, Maxime Argoud, Jerome Hazart, Patricia Pimenta-Barros, Aurelien Sarrazin, Nicolas Posseme, Raluca Tiron, Xavier Chevalier, Celia Nicolet, Christophe Navarro

JM3, Vol. 15, Issue 03, 031604, (August 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.3.031604

KEYWORDS: Directed self assembly, Annealing, Polymethylmethacrylate, Line width roughness, Picosecond phenomena, Semiconducting wafers, Lithography, Optical lithography, Image registration, Plasma

Read Abstract +

Proceedings Article | 23 March 2016 Paper

PMMA removal selectivity to PS using dry etch approach: sub-10nm patterning application

A. Sarrazin, N. Posseme, P. Pimenta Barros, S. Barnola, G. Claveau, A. Gharbi, M. Argoud, G. Chamiot-Maitral, R. Tiron, C. Nicolet, C. Navarro, C. Cardinaud

Proceedings Volume 9782, 97820G (2016) https://doi.org/10.1117/12.2220586

KEYWORDS: Directed self assembly, Polymethylmethacrylate, Chemistry, Picosecond phenomena, Etching, Xenon, Plasma, Carbon monoxide, Plasma etching, Semiconducting wafers

Read Abstract +

Proceedings Article | 21 March 2016 Paper

Surface affinity role in graphoepitaxy of lamellar block copolymers

G. Claveau, P. Quemere, M. Argoud, J. Hazart, P. Pimenta Barros, A. Sarrazin, N. Posseme, R. Tiron, X. Chevalier, C. Nicolet, C. Navarro

Proceedings Volume 9779, 97791F (2016) https://doi.org/10.1117/12.2219131

KEYWORDS: Line width roughness, Polymers, Directed self assembly, Optical lithography, Line edge roughness, 193nm lithography, Semiconducting wafers, Statistical analysis, Polymer thin films, Annealing, Polymethylmethacrylate, Lithography, Image registration, Photomasks

Read Abstract +

Proceedings Article | 17 March 2015 Paper

DSA planarization approach to solve pattern density issue

P. Pimenta Barros, A. Gharbi, Aurélien Sarrazin, R. Tiron, N. Posseme, S. Barnola, S. Bos, C. Tallaron, G. Claveau, X. Chevalier, M. Argoud, Isabelle Servin, C. Navarro, Célia Nicolet, C. Lapeyre, C. Monget

Proceedings Volume 9428, 94280D (2015) https://doi.org/10.1117/12.2086810

KEYWORDS: Polymethylmethacrylate, Etching, Critical dimension metrology, Picosecond phenomena, Semiconducting wafers, Chemistry, Scanning electron microscopy, Carbon monoxide, Dry etching, Directed self assembly

Read Abstract +

Proceedings Article | 28 March 2014 Paper

Plasma etching and integration challenges using alternative patterning techniques for 11nm node and beyond

S. Barnola, P. Pimenta Barros, C. Arvet, C. Vizioz, N. Posseme, A. Gharbi, M. Argoud, R. Tiron, J. Pradelles, L. Desvoivres, S. Barraud

Proceedings Volume 9054, 90540E (2014) https://doi.org/10.1117/12.2046251

KEYWORDS: Etching, Electron beam lithography, Polymethylmethacrylate, Silicon, Picosecond phenomena, Photomasks, Chemistry, Lithography, System on a chip, Metals

Read Abstract +

Proceedings Article | 17 March 2012 Paper

Towards new plasma technologies for 22nm gate etch processes and beyond

O. Joubert, M. Darnon, G. Cunge, E. Pargon, D. Thibault, C. Petit-Etienne, L. Vallier, N. Posseme, P. Bodart, L. Azarnouche, R. Blanc, M. Haas, M. Brihoum, S. Banna, T. Lill

Proceedings Volume 8328, 83280D (2012) https://doi.org/10.1117/12.920312

KEYWORDS: Plasma, Etching, Silicon, Ions, Plasma etching, Semiconducting wafers, Silica, Oxides, Oxidation

Read Abstract +

Showing 5 of 14 publications

Conference Committee Involvement (9)

Advanced Etch Technology and Process Integration for Nanopatterning XII

28 February 2023 | San Jose, California, United States

Advanced Etch Technology and Process Integration for Nanopatterning XI

26 April 2022 | San Jose, California, United States

Advanced Etch Technology and Process Integration for Nanopatterning X

22 February 2021 | Online Only, California, United States

Advanced Etch Technology for Nanopatterning IX

25 February 2020 | San Jose, California, United States

Advanced Etch Technology for Nanopatterning VIII

25 February 2019 | San Jose, California, United States

Showing 5 of 9 Conference Committees

Keywords/Phrases

Search In:

Publication Years