As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.
Ingrid De Wolf, Jeroen De Coster, Vladimir Cherman, Piotr Czarnecki, Stanislaw Kalicinski, Olalla Varela Pedreira, Sandeep Sangameswaran, Kris Vanstreels
In this paper various non-standard methods and instruments for the functional, yield and reliability analysis of MEMS
are discussed. Most of these methods are based on existing instruments, involving electrical, optical or mechanical
measurements. We present either alternative applications of existing techniques, new methodology for data extraction, or
adaptation/automation of the techniques for automatic chip or wafer level measurements.
This paper presents two distinct measurement systems that were custom-built for the parametric and functional yield
inspection of MEMS devices on wafer-level. Throughput as well as accuracy was optimized by using automatic feature
detection and data segmentation algorithms. Inaccuracies in stage positioning during scanning are compensated for by a
grid detection algorithm. The analysis of the measurement data is performed in parallel with the ongoing measurements.
The data analysis includes the detection, parameter extraction, analysis of failures or damage of a single device and the
final stitching of the results in order to obtain a visual mapping of the measured arrays. The performance of both systems
has been demonstrated using arrays of micromirrors as test vehicles.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.