ASELSAN, the largest defense company in Türkiye, develops high performance electro-optical systems for various applications. Research and development activities have been carried out on developing HgCdTe (MCT) detectors for long-wavelength infrared (LWIR) and mid-wavelength infrared (MWIR). In this paper, recent results for VGA 15μm pitch MWIR MCT detectors at IDDCA level are presented. P-on-n MCT epilayers are used for FPA fabrication with either mesa or planar pixel structures. Typically, over 99% operability and less than 20mK NETD values are achieved for 15μm pitch 640x512 format MWIR MCT FPAs at IDDCA level (F/4) in a repeatable fashion. Thermal cycle, mechanical shock, vibration and environmental tests (such as storage and operation under hot and cold temperatures) were applied to these MWIR MCT IDDCAs and passed successfully. Besides ongoing efforts on development of FPAs with 15μm pixel pitch, development activities for pixel pitch reduction also initiated recently for MWIR MCT and very promising results are achieved.
A 1280x1024 Readout Integrated Circuit (ROIC) with 15 μm pixel pitch for MWIR and LWIR applications is designed in 0.18 μm CMOS process. Integrate-Then-Read (ITR) and Integrate-While-Read (IWR) configurations are supported in snapshot mode. The ROIC pixel topology is direct injection (DI) with 3-bit programmable pixel gain. The minimum charge capacity is 0.8 Mé and the maximum full-well-capacity (FWC) is more than 13.2 Mé in ITR mode. 2, 4, 8, and 16 analog video output modes are also supported with a maximum frame rate of 240 fps at 16-output mode. A digital serial interface is used to program timing registers and analog biases. Integration time is programmable with 0.1 μs resolution up to 429 second using 10 MHz clock frequency. The pixel supports binning, windowing and anti-blooming functions. Digital and analog blocks of the ROIC operates using 1.8V and 3.3V supplies. The power consumption is less than 175 mW in 4-output mode of operation at 30 fps.
ASELSAN, the largest defense company in Turkey, develops high performance electro-optical systems for various applications. Due to the technical challenges and relatively higher cost associated with MCT technology, there is a search for an alternative material system all over the world, especially for the applications that need relatively low quantum efficiency and high volume production. Research and development activities have been carried out on developing InAs/GaSb T2SL detectors for mid-wavelength infrared (MWIR) technology in ASELSAN. In this paper, recent results for 15μm pitch MWIR T2SL and 10μm pitch MWIR T2SL detectors are presented. InAs/GaSb T2SL epilayers are used for FPA fabrication with mesa pixel structures. Typically, over 99% operability and less than 25 mK NETD values are achieved for 15 μm pitch 640x512 format MWIR T2SL FPAs at IDDCA level (F/4). Besides ongoing efforts on development of FPAs with 15 μm pixel pitch, development activities for pixel pitch reduction are also initiated recently for MWIR T2SL FPAs for improving resolution and promising results are achieved. For this purpose, MWIR T2SL FPAs with 1280x1024/10μm resolution/pixel pitch are fabricated and NETD values less than 25 mK (F/2) with pixel operability of 97% are achieved for the first prototypes.
Recent advances in short-wave infrared (SWIR) technology including numerous new applications in civil areas, fusion with visible wavelengths, and integration with active imaging systems triggered the SWIR photodetector research at ASELSAN for both passive and active imaging. SWIR focal plane arrays with a 640x512 format and 15μm pitch were developed and coupled with ASEL64015C readout circuits which had been designed at ASELSAN as well. Through extensive research and development dark current density values <10 nA/cm2 (at 20°C) and operabilities >;99% were achieved. This paper reviews the work that has been conducted on SWIR detector development at ASELSAN.
Microbolometer detector development and production processes have been studied intensely at ASELSAN for the last several years. Researches have been conducted so as to develop uncooled Focal Plane Arrays (FPAs) with high resolution and smaller pixel pitch. Test results show that SAFIR640 detectors have high performance level and low time constant which make them ideal for military and civilian applications. SAFIR640 microfabrication has been performed on 8’’ CMOS ROIC wafers which are also designed by ASELSAN. A double layer 17 μm pitch microbolometer structure is designed with an active material layer of VOx. 640×480 format SAFIR640 detectors with high TCR and low noise level are successfully fabricated and integrated into a TEC-less system. The produced detectors have low NETD (<30 mK) and low time constant values (<12 ms) values according to the test results. In this paper, electro-optical characterizations and the performance measurements of the SAFIR640 detectors have been presented.
A 10μm pixel pitch 1280×1024 Readout Integrated Circuit (ROIC) for MWIR applications is designed and fabricated using 0.18 μm CMOS process. It operates in snapshot mode supporting both Integrate-Then-Read (ITR) and IntegratedWhile-Read (IWR) configurations. The ROIC pixel has direct injection (DI) input stage and provides 2-bit programmable pixel gain. It has a minimum charge capacity of 0.7 Mé and a maximum full-well-capacity (FWC) of more than 6.3 Mé in ITR mode. 4, 8 and 16 analog video output modes are also supported with a maximum frame rate of 120 fps at 16-output mode. All digital timing and analog biasing are programmable through a serial interface. Integration time is programmable with 0.1 μs resolution by internal timing circuitry. It supports binning, windowing and antiblooming functions. The ROIC operates with 3.3 V and 1.8 V supplies and dissipates less than 175 mW in 4-output mode of operation at 30 fps. An Analog-Front-End (AFE) card is designed to operate the ROIC and convert analog video outputs into 14-bit digital value. Digitized video data is further processed by 1-point and 2-point Non-Uniformity Correction (NUC), histogram equalization and bad pixel replacement algorithms. The ROIC has been tested with a prototype FPA at 77K. Measurement results of ASEL128010 indicate that it is functional at all operating modes including windowing and binning. The input referred noise level of the ROIC is 877 é at 6.3 Mé FWC.
Microbolometer detectors have drawn attention due to their advantages such as small dimensions, light weight, low power consumption and no cooling requirement. In recent years, studies regarding the microbolometers have accelerated. Research on uncooled infrared microbolometer detectors was initiated at ASELSAN in 2014. As result of these activities, microbolometers with high TCR and low 1/f noise level have been achieved based on vanadium oxide active material. Pixel structures with high fill factor ratios are accomplished using double layer pixel architecture and high responsivity values were obtained by FPA optimizations. 640 x 480 format and 17 μm pixel pitch microbolometer FPAs along with VOx sensing layer were produced. These detectors have demonstrated state of the art NETD values (< 30 mK @ f/1) and with such properties that could be used in various applications which require high frame rates due to their low time constant values (< 12 ms). FPA fabrication has been performed on 8” CMOS ROIC wafers which are also designed by ASELSAN. 17 μm pixel pitch 640 x 480 format ROIC has been developed for resistive microbolometer detector arrays. ROIC wafers were fabricated using 0.18 μm CMOS process where 3.3 V analog and 1.8 V digital supplies are used. The ROIC has 4 analog video outputs and 2 analog reference outputs. It can be operated at 1, 2 or 4 output modes depending on the frame rate requirement. In 2-output mode of operation power consumption of the ROIC is less than 150 mW. In this paper, the details of the microbolometer detectors including the ROIC design, vacuum packaging and detector performances are presented.
ASELSAN A.S., the largest defense company in Turkey, develops high performance electro-optical systems for land, air and naval applications. Research activities on developing Mercury Cadmium Telluride (MCT) detectors are on-going for MW and LW infrared bands. In this paper, recent results on Cadmium Zinc Telluride substrate growth, long wavelength (LW) Mercury Cadmium Telluride (MCT) detector fabrication and readout integrated circuit design are summarized. LW MCT focal plane arrays with a format of 320×256/30 μm are fabricated. Noise Equivalent Temperature Difference (NETD) of these focal plane arrays (FPA) are 45.7 mK and 59.9 mK (f/1.5, 77K) while the operabilites are 98.14% and 99.28%, respectively.
This paper reports a 640x512 SWIR ROIC with 15um pixel pitch that is designed and fabricated using 0.18um CMOS process. Main challenge of SWIR ROIC design is related to input circuit due to pixel area and noise limitations. In this design, CTIA with single stage amplifier is utilized as input stage. The pixel design has three pixel gain options; High Gain (HG), Medium Gain (MG), and Low Gain (LG) with corresponding Full-Well-Capacities of 18.7ké, 190ké and 1.56Mé, respectively. According to extracted simulation results, 5.9é noise is achieved at HG mode and 200é is achieved at LG mode of operation. The ROIC can be programmed through an SPI interface. It supports 1, 2 and 4 output modes which enables the user to configure the detector to work at 30, 60 and 120fps frame rates. In the 4 output mode, the total power consumption of the ROIC is less than 120mW. The ROIC is powered from a 3.3V analog supply and allows for an output swing range in excess of 2V. Anti-blooming feature is added to prevent any unwanted blooming effect during readout.
A 15 μm pixel pitch 640×512 Readout Circuit (ROIC) for MWIR applications is designed and fabricated using 0.18 um CMOS process. The ROIC is implemented using Direct Injection (DI) input stage with programmable pixel gain where maximum full-well-capacity (FWC) is more than 13Mé. All analog current and voltage bias values can be programmed through a digital interface. Additionally, integration time can be programmed with 0.1 µsec resolution by internal timing circuitry. ROIC has 1, 2 and 4 output modes with a frame rate of 120fps at 4 output mode. The design supports IntegrateThen-Read (ITR) and Integrate-While-Read (IWR) modes in snapshot operation. Photodetector reverse bias voltage is controlled by adjusting the bias of the common-gate input stage at the input of DI pixel. An on-chip low-dropout voltage regulator is used to generate the detector common voltage. With 2x2 binning feature, the ROIC can also be used for 30 µm pixel pitch 320x256 photodetector arrays. An Analog-Front-End (AFE) card has been designed to operate the ROIC and to convert analog video output to a 14-bit digital value. This digital video data is handled by external video processor card which supports 1-point and 2-point Non-Uniformity Correction (NUC), histogram equalization, bad pixel replacement and filtering. The ROIC has been extensively tested with a prototype FPA at 77°K. According to these test results, functionality of all modes have been verified and a noise level of 700é is achieved at 4.5Mé FWC.
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