The processing of gate-all-around (GAA) Si transistors requires several isolated and vertically stacked nanometer-thick Si sheets or wires. For this purpose, the sacrificial SiGe layers of a SiGe/Si superlattice are etched selectively and laterally. Controlling the quantity of etched SiGe material, i.e., the so-called SiGe cavity depth, is critical for optimal device performance. Unfortunately, this critical dimension can only be measured by time-consuming cross-sectional transmission electron microscopy (TEM), which results in limited statistics and hence insufficient control of the cavity depth across wafers and batches. This paper evaluates the capabilities of micro hard x-ray fluorescence (μHXRF) for the determination of cavity depth as a fast and non-destructive alternative to TEM. As we show, μHXRF provides cavity depth values in excellent agreement with TEM. In addition, two critical advantages of the technique demonstrated here are that, thanks to the very high energy of the incoming and emitted X-rays, the SiGe volume is extracted without requiring any complex model and without any correlation to other geometrical parameters of the complex GAA device.
For enabling better electrostatic control of short channel devices, gate-all-around (GAA) nanowire/nanosheet (NW/NS) field-effect transistors (FETs) may replace FinFET in 3nm logic technology node and beyond. Horizontally stacked NW/NS FETs are especially promising due to its excellent electrostatics, short channel control, increased active width, and gate length scaling. In order to enable further scaling of GAA FETs, imec has been developing forksheet (FS) FET as well as complementary FET (CFET).
For the manufacturing of FS and CFETs, there are several new challenges which require isotropic and selective etching. In this work, we have been developed chemical isotropic dry etching for the several key process steps along with the integration flow, including Si/SiGe superlattice fin reveal, dielectric wall formation, local SOI formation, SiGe cavity etch as well as the dielectric etchback for the inner spacer formation, dummy gate removal and SiGe selective etch for the Si channel release
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