Data volume and average data preparation time continue to trend upward with newer technology nodes. In the past decade, with file sizes measured in terabytes and network bandwidth requirements exceeding 40GB/s, mask synthesis operations have expanded their cluster capacity to thousands and even 10s of thousands of CPU cores. Efficient, scalable and flexible management of this expensive, high performance, distributed computing system is required in every stage of geometry processing - from layout polishing through Optical Proximity Correction (OPC), Mask Process Correction (MPC) and Mask Data Preparation (MDP) - to consistently meet tape out cycle time goals. The MDP step, being the final stage in the entire flow, has to write all of the pattern data into one or more disk files. This extremely I/O intensive section remains a significant portion of the processing time and creates a major challenge for the software from a scalability perspective. It is important to have a comprehensive solution that displays high scalability for large jobs and low overhead for small jobs, which is the ideal behavior in a typical production environment. In this paper we will discuss methods to address the former requirement, emphasizing the efficient use of high performance distributed file systems while minimizing the less scalable disk I/O operations. We will also discuss dynamic resource management and efficient job scheduling to address the latter requirement. Finally, we will demonstrate the use of a cluster management system to create a comprehensive data processing environment suitable to support large scale data processing requirements.
With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.
With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 1, 5] show that even though the intrafield component stays the same this becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. To improve focus margin, a study has been started to determine if some correlations between scanner levelling performance, product layout and topography can be observed. Both topography and levelling intrafield fingerprints show a large systematic component that seems to be product related. In particular, scanner levelling measurement maps present a lot of similarities with the layout of the product. The present paper investigates the possibility to model the level sensor’s measured height as a function of layer design densities or perimeter data of the product. As one component of the systematics from the level sensor measurements is process induced topography due to previous deposition, etching and CMP, several layer density parameters were extracted from the GDS’s. These were combined through a multiple variable analysis (PLS: Partial Least Square regression) to determine the weighting of each layer and each parameter. Current work shows very promising results using this methodology, with description quality up to 0.8 R2 and expected prediction quality up to 0.78 Q2. Since product layout drives some intrafield focus component it is also important to be able to assess intrafield focus uniformity from post processing. This has been done through a hyper dense focus map experiment which is presented in this paper.
The link between wafer manufacturing and wafer test is often weak: without common information system, Test
engineers have to read locations of test structures from reference documents and search them on the wafer prober screen.
Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing
sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer
locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help
to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can
simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera
views and design database used for wafer manufacturing. As proven by several augmented reality applications, like
Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to
understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high
integration of these machines with their control panel. But many existing software libraries could be used to plot the
design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39
standard); multiple free software and commercial viewers/editors/libraries for these formats are available.