With the adoption of multi-beam mask writing (MBMW) technology, there is a strong drive to realize the maximum lithographic process window entitlement which can be obtained with curvilinear masks, including both SRAFs and main features. Inverse Lithography Technology (ILT) has always featured prominently in planning for such masks, as it can produce the ideal curvilinear patterns which represent the best possible solution. The runtime for ILT, however, remains too slow for full-chip logic manufacturing and this paper will review multiple alternative approaches which endeavor to produce similar output masks but with significantly faster runtime. Results will be shown for 3nm-node via and metal examples where full ILT, hybrid ILT and dense curvilinear OPC, hybrid curvilinear SRAF and dense curvilinear OPC, and machine learning approaches will be assessed for runtime and a variety of lithographic metrics. Overall, all solutions are shown to be considerably faster than full ILT, ranging between 4x (for hybrid ILT SRAF) to <100X improved runtime performance. Lithographic capability is characterized in terms of distributions of edge placement errors (EPE), PV Bands, and ILS/NILS. There are some minor differences between the various options, but given the pronounced runtime advantages over ILT, all are compelling options, delivering lithographic PW enablement close to the ideal ILT solution. For the model-based DNN, and Monotonic Machine Learning (MML) approaches, we will discuss the approach, challenges, and advantages associated with robust training to ensure the broadest possible pattern coverage.
Key factors for maximizing yield in a modern semiconductor fab for Memory device manufacturing include wafer critical dimension uniformity and accuracy control. Resolution Enhancement Techniques (RET) solutions for the highly repetitive arrayed memory devices have been driven by the need for perfect geometric consistency without compromising the lithographic quality. Traditionally, both optical proximity correction (OPC) and sub-resolution assist features (SRAFs) insertion for these repetitive cell-array structures have been dealt by applying manual hand-crafted or rule-based methods. But these can be prone to iterative human intervention, long runtimes and sub-par lithographic quality. This work adopts a pattern/property aware approach (PA)2 and cell-array OPC technology that leverage the inherent repetitive and hierarchical structure of the cell-array to ensure the lithographic quality and perfect geometric consistency and symmetry down to the level of feature edges with model-based OPC and rule-based SRAF solutions. The flow also demonstrates a drastic reduction in runtime and turn-around-time to mask tapeouts for the full chip (core and periphery).
Sub-Resolution Assist Features (SRAFs) have emerged as a key technology to enable semiconductor manufacturing for advanced technology nodes. SRAF placement is required to adhere to manufacturability constraints (MRC). MRC specifications are distance and size constraints specified by the user to ensure SRAFs are not detrimental to the final target shapes being printed. Conceptually, SRAF placement can be divided into two steps - SRAF candidate generation and SRAF candidate cleanup or conflict resolution. SRAFs generated as candidates may not adhere to MRC constraints. It is during the cleanup/conflict resolution process that the MRC constraints are enforced. In this paper we focus on the latter phase - cleanup. The goal of the cleanup phase is to retain as much of the initial candidates as possible, and, if necessary, transform them to adhere to MRC conditions. An SRAF is said to be in conflict with another shape if it violates the distance MRC constraint. One can model these conflicts using a conflict graph G=(V,E), whose vertices V correspond to geometric shapes involved in a conflict and an edge is present in E, between two vertices if the corresponding shapes are involved in a conflict. A weight is associated with each vertex that could, for example, correspond to area of the corresponding shape. The goal of conflict resolution then, is to find a transformation of the vertices so that the resulting graph is conflict free while maximizing the weight of vertices retained. This can be viewed as a generalization of the computationally hard problem of finding the largest independent set of candidates, albeit allowing for transformation. The transformations we allow include deletion, splitting, resizing, merge, and bounded translation. In this paper, we describe an approach which classifies the conflicts and apply appropriate transformations to achieve effective SRAF placement. Further, we demonstrate that such a strategy reduces the number of rules to be specified by the user, reducing the user effort needed to achieve desirable imaging results.
Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.
Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.
Source Mask Optimization (SMO) has become an integral part of resolution enhancement techniques (RET) for almost all critical layers at advanced technology nodes. Over the past couple of years, various flows have emerged for integrating SMO into mainstream RET selection. These flows revolve mainly around clip selection, resist model, verification and analysis metrics, design rule optimization, and so on. There has also been strong emphasis on the quality of mask that is conjugated for source selection process. All these variations in analysis and rigorous simulations for flow selection are critical but they also create a bottleneck in overall RET development. In this paper, we demonstrate an initial RET development flow for 20 nm technology with emphasis on quantifying benefits coming from source and mask. We also report challenges that are encountered in the foundry environment when moving from RET development to production. In conclusion, we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for a production environment.
With 20nm production becoming a reality, research has started to focus on the technology needs for 14nm. The LELE
double patterning used in 20nm production will not be able to resolve M1 for 14nm. Main competing enabling
technologies for the 14nm M1 are SADP, EUV, and LELELE (referred as LE3 thereafter) triple patterning.
SADP has a number of concerns of 1. density, as a layout geometry needs to stay complete as a whole, and can not be
broken; 2. the complexity in SADP mask generation and debug feedback to designers; 3. the subtraction nature
of the trim mask further complicates OPC and yield. While EUV does not share those concerns, it faces significant
challenges on the manufacturing equipment side.
Of the SADP concerns, LE3 only shares that of complexity involved in mask generation and intuitive debug
feedback mechanism. It does not require a layout geometry to stay as a whole, and it benefits from the affinity to
LELE which is being deployed for 20nm production. From a process point of view, this benefit from affinity to LELE
is tremendous due to the data and knowledge that have been collected and will be coming from the LELE deployment.
In this paper, we first recount the computational complexity of the 3-colorability problem which is an integral
part of a LE3 solution. We then describe graph characteristics that can be exploited such that 3-colorability
is equivalent under divide-and-conquer. Also outlined are heuristics, which are generally applied in solving
computationally intractable problems, for the 3-colorability problem, and the importance in choosing appropriate
worst-case exponential runtime algorithms. This paper concludes with a discussion on the new hierarchical problem
that faces 3-colorability but not 2-colorability and proposals for non-3-colorability feedback mechanism.
Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal
layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various
solutions.
○ We examine DP design methodologies, current DP conflict feedback mechanisms, and how they can help
designers identify and resolve conflicts.
○ In place and route (P&R), the placement engine must now be aware of the assumptions made during IP cell
design, and use placement directives provide by the library designer. We examine the new effects DP
introduces in detail routing, discuss how multiple choices of LELE and the cut allowances can lead to different
solutions, and describe new capabilities required by detail routers and P&R engines.
○ We discuss why LELE DP cuts and overlaps are critical to optical process correction (OPC), and how a hybrid
mechanism of rule and model-based overlap generation can provide a fast and effective solution.
○ With two litho-etch steps, mask misalignment and image rounding are now verification considerations. We
present enhancements to the OPCVerify engine that check for pinching and bridging in the presence of DP
overlay errors and acute angles.
Sub-Resolution Assist Features (SRAFs) have been extensively used to improve the process margin for isolated and
semi-isolated features. It has been shown that compared to rule-based SRAFs, model-based placement of SRAFs can
result in better overall process window. Various model-based approaches have been reported to affect SRAF placements.
Even with model-based solutions, the complexity of two-dimensional layouts results in SRAF placement conflicts,
producing numerous challenges to optimal SRAF placement for each pattern configuration. Furthermore, tuning of
SRAF placement algorithms becomes challenging with varying patterns and sources [1-3].
Recently, pixelated source in optical lithography has become the subject of increased exploration to enable 22/20 nm
technology nodes and beyond. Optimization of the illumination shape, including free-form pixelated sources, has shown
performance gains, compared to standard source shapes [4-6]. This paper will demonstrate the influence of such
different free-form sources as well as conventional sources on model-based SRAF placement. Typically in source
optimization, the selection of the optimization patterns is exigent since it drives the source solution. Small differences in
the selected patterns produce subtle changes in the optimized source shapes. It has also been previously reported that
SRAF placements are significantly dependent on the illumination [1]. In this paper, the impact of changes in the design
and/or source optimization patterns on the optimized source and hence on the SRAF placement is reported. Variations in
SRAF placements will be quantified as a function of change in the free-form sources. Lithographic performance of the
different SRAF placement schema will be verified using simulation.
Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for
isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically
been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional
rules govern the relationship of assist features to one another, and for random logic contact layers, the
overall ruleset can become rather complex. It has been shown that model-based placement of SRAFs for
contact layers can result in better worst-case process window than that obtained with rules, and various
approaches have been applied to affect such placement. The model comprehends the specific illumination
being used, and places assist features according to that model in the optimum location for each contact
hole. This paper examines the impact of various illumination schemes on model-based SRAF placement,
and compares the resulting process windows. Both standard illumination schemes and more elaborate
pixel-based illumination pupil fills are considered.
Double patterning is one of the main enabling technologies for expanding lithography beyond 45nm technology node.
Geometric pitch split and litho friendly design is the core of double patterning. There has been lot of development
recently in area of DP to minimize split errors and hot spots. In this paper we demonstrate one such application of
predictive modeling to detect hot spots. The matrix for pitch splitting is developed at higher resolution wavelengths in
design stage and the decomposed results are evaluated with different source types. This type of predictive model
confronts hot spot information and un-resolvable pitches in design stage and assists in developing restricted design rules
for litho friendly design.
LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong
candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization
when design is not manufacturable with DPT and mask assignment either when it is or despite it is not.
Concurrent with the advancements in double patterning process, there has been active research [1] [2] [3] [4]
addressing the problem of mask planning. As geometries across the chip can potentially involve in the same
conflict, DPT decomposition has been recognized as unbounded [5] [4]. We will show in this paper that the
unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle
to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels
of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of
fully flattened design are even more amenable in that they are already positioned with respect to the flat view,
and tiles overlap only marginally when they do.
While there have been ample research literature in the mask assignment problem with respect to geometries
within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special
handling needed for peculiar complexities arising from the presence of hierarchy [5] [6]. Hierarchy adds a subtle
but significant dimension to the mask planning problems. This paper investigates contact layer mask planning
for DPT, and presents results on two new problems due to hierarchical processing.
Scatter Bar (SBAR) insertion is a computationally expensive operation. SBAR are usually generated rule-based. SBAR rule tables dictate the insertion of SBAR with different SBAR width dependent on the width of the printable main features and the spacing between the main features and SBAR. Optimization of the SBAR rules drives manufactures to ever more complex SBAR tables which increase the runtime. In advanced process nodes, SBAR printing issues, missing SBAR due to clean-up problems and joining SBAR of different width together remain challenging. On the other hand, pixelized inversion methods may yield optimized SBAR solutions, especially in terms of SBAR placement for contact layers, but comes at the expense of significant computational effort and increased mask writing and inspection time. Since OPC changes the spacing between SBAR and main features, an accurate and optimized SBAR solution requires OPC and SBAR optimization to run interactively.
This work focuses on both line/space and contact layers To ensure fast SBAR optimization, SBAR placement and SBAR width optimization are separated. SBAR of uniform width are placed fast driven by a simple rule-based table comprising only a single SBAR width. This intermediate SBAR layer is subject into a model-based approach, which fragments the SBAR layer based on proximity with respect to the main features or other SBAR, and assigns measurement sites to each SBAR fragment. A model is used to move each SBAR fragment inward or outward so that the image cut line shows a maximum SBAR intensity closer to a predefined SBAR printing threshold. While the main features are unchanged, several iterations are applied to converge the SBAR fragments. Keeping the SBAR fragments fixed, OPC is applied to the main features. Repeating these steps allows optimization of the SBAR width and the OPC simultaneously. Site based as well as contours based verification methods are applied to ensure that the SBAR printing margin has been significantly improved. The improved SBAR printing margin allows manufactures to apply more aggressive SBAR placement rules, which, in addition to the optimized SBAR width, helps to enlarge the depth of focus, therefore, widen the common process window of the lithography process.
For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable
printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion
scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the
minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch
to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole
illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic,
interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical
features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal
features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then
applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid
problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the
original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout
by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these
issues.
Conventional OPC, also known as site-based OPC, has relied on rules-based fragmentation and site placement since its inception. The issues that arose in earlier generations around imprecise site and fragmentation placement, relative to the exact location of proximity effects, has been illustrated in earlier works [1] but generally did not produce catastrophic results. However, when coupled with the large process biases, strong RET, and accuracy requirements for 45 nm and future nodes, this imprecision can produce catastrophic results. This work will report on efforts to use model-directed site and fragmentation placement, as well as inclusion of process window knowledge into the site-based OPC flow to address varied sources of errors and relative results with different approaches.
In addition to the conventional site-based OPC, a new breed of tool that avoids sites in favor of fully gridded, or dense, simulation is rapidly maturing. The new approach allows more intelligence to be built into the OPC engine such that fragmentation and error sampling are more automated and thus less error prone. Using the same layout data, we will also present a snapshot of the new tool's results.
Current state-of-the-art OPC (optical proximity correction) for 2-dimensional features consists of optimized
fragmentation followed by site simulation and subsequent iterations to adjust fragment locations and
minimize edge placement error (EPE). Internal and external constraints have historically been available in
production quality code to limit the movement of certain fragments, and this provides additional control for
OPC. Values for these constraints are left to engineering judgment, and can be based on lithography
process limitations, mask house process limitations, or mask house inspection limitations. Often times
mask house inspection limitations are used to define these constraints. However, these inspection
restrictions are generally more complex than the 2 degrees of freedom provided in existing standard OPC
software. Ideally, the most accurate and robust OPC software would match the movement constraints to
the defect inspection requirements, as this prevents over-constraining the OPC solution.
This work demonstrates significantly improved 2-D OPC correction results based on matching movement
constraints to inspection limitations. Improvements are demonstrated on a created array of 2D designs as
well as critical level chip designs used in 45nm technology. Enhancements to OPC efficacy are proven for
several types of features. Improvements in overall EPE (edge placement error) are demonstrated for
several different types of structures, including mushroom type landing pads, iso crosses, and H-bar
structures. Reductions in corner rounding are evident for several 2-dimensional structures, and are shown
with dense print image simulations. Dense arrays (SRAM) processed with the new constraints receive
better overall corrections and convergence. Furthermore, OPC and ORC (optical rules checking)
simulations on full chip test sites with the advanced constraints have resulted in tighter EPE distributions,
and overall improved printing to target.
The OPC treatment of aerial mage ripples (local variations in aerial contour relative to constant target edges) is one of the growing issues with very low-k1 lithography employing hard off-axis illumination. The maxima and minima points in the aerial image, if not optimally treated within the existing model based OPC methodologies, could induce severe necking or bridging in the printed layout. The current fragmentation schemes and the subsequent site simulations are rule-based, and hence not optimized according to the aerial image profile at key points. The authors are primarily exploring more automated software methods to detect the location of the ripple peaks as well as implementing a simplified implementation strategy that is less costly. We define this to be an adaptive site placement methodology based on aerial image ripples. Recently, the phenomenon of aerial image ripples was considered within the analysis of the lithography process for cutting-edge technologies such as chromeless phase shifting masks and strong off-axis illumination approaches [3,4]. Effort is spent during the process development of conventional model-based OPC with the mere goal of locating these troublesome points. This process leads to longer development cycles and so far only partial success was reported in suppressing them (the causality of ripple occurrence has not yet fully been explored). We present here our success in the implementation of a more flexible model-based OPC solution that will dynamically locate these ripples based on the local aerial image profile nearby the features edges. This model-based dynamic tracking of ripples will cut down some time in the OPC code development phase and avoid specifying some rule-based recipes. Our implementation will include classification of the ripples bumps within one edge and the allocation of different weights in the OPC solution. This results in a new strategy of adapting site locations and OPC shifts of edge fragments to avoid any aggressive correction that may lead to increasing the ripples or propagating them to a new location. More advanced adaptation will be the ripples-aware fragmentation as a second control knob, beside the automated site placement.
One of the enabling RET candidates for 45 nm robust imaging is high transmission (20-30%) EAPSM masks. However, the effectiveness of these masks is strongly affected by the electromagnetic field (EMF) that is ignored in most commercial full-chip OPC applications that rely on the Kirchhoff approximation. This paper utilizes new commercial software to identify and characterize points in a design that are especially sensitive to these EMF effects. Characterization of conventional 6% and 30% High Transmission photomasks were simulated and compared with experimental results. We also explored, via simulation-driven design of experiment, the impact of mask variations in transmission, phase, and SRAF placement and size to the imaging capability. The simulations are confirmed by producing a photomask including the experimental variations and printing the mask to silicon. Final analysis of the data will include exact mask measurements to confirm match to simulation assumptions of mask stack, and phase.
The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.
Traditional model based OPC software operates under a set of simple guiding principles. First, a design is fragmented into finitely sized segments, the sizes and numbers of which are limited by run-time and mask constraints. Within each fragment the intensity profile (aerial image) and edge-placement error (EPE) are calculated at a single location. Finally, the length of the entire fragment is moved to correct for the EPE at that location. This scheme has potential limitations in certain cases. For instance, cases where the aerial image contour (and therefore EPE) vary at a higher frequency than the minimum allowed fragmentation frequency. This so-called aerial image ripple problem can challenge the abilities of simple model based OPC. In addition, certain advanced RET schemes require that EPE be controlled in areas that have no adjacent mask polygon. Similarly, certain double-exposure RETs require the mutual optimization of features on multiple mask layers. Our paper will describe a flexible model based OPC scheme called Matrix OPC, which has proven capabilities of resolving these and many other advanced RET problems.
It has been published that there is potential benefit to utilizing an OPC model based upon defocus instead of best focus processing, to give more robust patterning. While this is true with respect to gross opens and bridging problems, the available CD budget and the anticipated manufacturing consumption of defocus budgets must be considered. The net result will almost certainly always be that for gate layer processing, defocus model based OPC is not desirable. For other layers there may be favorable yield implications to running in such a manner, but the average CD in manufacturing will deviate from the design target. This paper will explore the interplay between variable focus distributions in manufacturing and the required CD control, pointing to those conditions under which a defocus model is advisable, and where it is not. Furthermore, the optimum magnitude of defocus is a compromise and has implications for final electrical performance.
This paper investigates variability across multiple lithographic domains, as experienced in typical manufacturing environments, and assesses the impact on achievable post-OPC image fidelity and CD control. Across scanner field and tool-tool effects are considered, and a distinction is made between systematic phenomena, which typically manifest within chip, and random fluctuations, which predominantly impact chip-to-chip mean distributions. The paper will outline which lithographic parameters can effectively be accounted for in OPC models, and over what temporal/spatial extents. The non-correctable phenomena assessed include misalignment, projection optic aberrations, illumination source profile, mask CD, focus and exposure dose variation, and flare. Specific analyses are applied to the case of gate edge placement error (EPE) control as a function of these manufacturing variables. Recommendations are made for "field-aware" metrology sample plans during model creation, such that globally optimized models can be realized. With knowledge of manufacturing input parameter variation, CalibreTM enables a detailed understanding of realistic post-OPC CD control, and can guide judicious product metrology sampling and specifications. It is highlighted that even for the case of a "perfect" OPC model, the post-OPC CD variation within chip can still be substantial, due to manufacturing variability.
AltPSM is a leading contender for the gate layer lithography at 65 nm, and perhaps additional layers at 45 nm. Every form of lithography varies in performance across dose and focus, but altPSM lithography also is subject to the impact of mask alignment and effective phase. In the past, these factors have been maintained to an acceptable level to achieve the required ACLV over an acceptable process window for the designs that warranted the additional expense of altPSM. As the ACLV requirements continue to shrink along with feature size, the control of these variables must also be tightened. This paper will illustrate a methodology of using silicon-calibrated models coupled with real layout to predict the variation in ACLV due to each of these process variations.
The ever-increasing complexity of integrated circuits and their enabling process technology has accelerated the increase in data volume of post-RET data which is input to the photomask manufacturing industry.
OASIS - the new stream format that has been developed by a working group under the sponsorship of the SEMI Data Path Task Force enables the representation of IC layout data in a much more compact form than GDSII and facilitates the incorporation of hierarchical data into the mask-making infrastructure. OASIS achieves on average a >10x reduction in file size compared to GDSII files and structures the data in a way, which allows a straightforward translation from a hierarchical format to the required flat mask perspective. Owing to the efficiency in representing the data, OASIS files are smaller than commonly used flat exchange formats - like MEBES, thus enabling an efficient hierarchical data flow both from the processing as well as the file handling prospective.
The implementation of OASIS into post-tapeout data flows will be discussed and experimental results on OASIS-based data preparation flows will be shown.
Much has been said of the impact that advanced RET and OPC are having on the mask manufacturing process. However, increasingly, the limitations of mask manufacturing are impacting the quality and effectiveness of advanced RET and OPC, and they do this often in unpredictable ways. Detection of when these constraints limit the success of RET/OPC before the mask is made is critical to achieving cost and schedule control. An understanding of the conditions under which sub-optimal solutions result is also a key aspect of early RET/OPC recipe development, since this is the time when more options exist for satisfactory resolution. It is therefore a requirement in both production and development to analyze, in both a qualitative and quantitative manner, the effectiveness of the RET/OPC procedures using the actual layout, where it has been applied. The paper will present a methodology for accomplishing this analysis at the full chip level, and demonstrate the results.
The data volumes of individual files used in the manufacture of modern integrated circuits have become unmanageable using existing data formats specifications. The ITRS roadmap indicates that single layer MEBES files in 2002 reached the 50 GB range, worst case. Under the sponsorship of SEMI, a working group was formed to create a new format for use in describing integrated circuit layouts in a more efficient and extendible manner. This paper is a report on the status and potential benefits the new format can deliver.
As the industry enters the development of the 65nm node the presssure on the data path and atepout flow is growing. Design complexity and increased deployment of RET resut in rapidly growing file sizes, which turned the commodity of mask data preparation into a real bottleneck. Mask manufacturing starting with the 130nm nodes is accompanied by an increasing depoloyment of variable shaped beam (VSB) mask writing machines. This transition requires the adaptation of the established data preparation path to these circumstances. Historicially data has been presented mostly in MEBES or similar intermediate formats to the mask houses. Reformatting these data is a redundant operation, which in addition is not very efficient given the constraints of the intermediate formats. An alternate data preparation flow accommodating the larger files and re-gaining flexibility for TAT and throughput management downstream is suggested. This flow utilizes the hierarchicial gds-format as the exchange format in the mask data preparation. The introduction of a hierarchical exchange format enables the transfer of a number of necessary data preparation steps into the hierarchical domain. The paper illustrates the benefit of hierarchical processing based on gds-files with experimental data on file size reduction and TAT improvement for direct format conversions vs. re-fracturing as well as other processing steps. In contrast to raster scan mask making equipment, in a variable shaped beam mask writing machine the writing time and the ability to meet tight mask specification is affected by data preparation. Most critical are the control of the total shot count, file size and the efficient suppression of small figures. The paper will discuss these performance parameters and illustrate the desired practices.
Due to the challenging CD control and resolution requirements of future device generations, a large number of complex lithography enhancement techniques are likely to be used for random logic devices. This increased design, reticle, process and OPC complexity must be handled flawlessly by process engineers in order to create working circuits. Additionally, the rapidly increasing cost and cycletime of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have extended the capability of leading edge model-based OPC software to find and analyze process-limiting regions in real product designs. Specifically, we have implemented and verified software usefulness to find design-process limitations due to measured lens aberrations, as well as errors in focus, exposure or reticle CD control. We present results showing the applications and limitations of these new model-based analysis methods to discover process-design interaction errors in 90nm and 130nm patterning processes; and to propose design rule, process or OPC improvements to mitigate these errors.
Progressing integration and system-on-chip approaches increase the complexity of advznce designs. Data preparation, mask and wafer manufacturing have to cope with these designs while achieving high throughput and tight specifications. One of the biggest variables in a production mask processing flow is the actual design being produced. Layout variability can invalidate process settings by introducing conditions outside of the range the process is calibrated for. Characterization of how parameters such as density distributions, CD distributions, minimium, and maximum CD impact yield will no doubt remain proprietary. However, the ability to characterize a layout by these geometric parameters as well as lithographic parameters is a common need. Gathering this knowledge prior to the processing can contribute significantly to the efficiency of applying process recipes once the correlation has been made. The capabilities of a statistical layout analysis are demonstrated and practical applications in mask data preparation and manufacturing are discussed.
As design rules shrink aggressively while the wavelength reduction in the exposure equipment cannot keep up, extensive usage of resolution enhancement techniques (RET) has complicated the generation and handling of mask writing data. Consequently, file size growth and computing times for mask data preparation rise beyond feasibility. In order to address these issues, an integrated flow has been developed. It starts out with the gds-file delivered by the backend of design and combines optical proximity correction, design rule and mask process rule verification, and all other necessary steps for mask data preparation into a single flow. The benefits of this strategy are time savings in data processing and handling, the elimination of intermediate files, and the elimination of data format interface issues. Since the new flow takes full advantage of the design hierarchy, file sizes shrink considerably and the whole data preparation infrastructure can be simplified. The paper will describe the transition to the new flow and quantify the benefits.
KEYWORDS: Photomasks, Manufacturing, Data processing, Resolution enhancement technologies, Lithography, Process control, Data conversion, Data storage, Optical proximity correction, Data communications
As the industry enters the development of the 65nm node the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which turns what used to be the relatively simple task of mask data preparation into a real bottleneck. This discussion introduces the data preparation scheme in the mask house and analyzes its evolution. Mask data preparation (MDP) has evolved from a flow that only needed to support a single mask lithography tool data format (MEBES) with minimal data alteration steps to one which requires the support of many mask lithography tool data formats and at the same time requires significant data alteration to support the increased precision necessary for today’s advanced masks.. However, the MDP flow developed around the MEBES format and it’s derivatives still exists. The design community has migrated towards the use of hierarchical data formats and processes to control file size and processing time. MDP, which from a file size and process complexity point of view is beginning to look more and more like the advanced RET operations performed on the data prior to mask manufacturing, is still standardized on a flat data format that is poorly optimized for a growing number of mask lithography tools. Based on examples it will be shown how this complicates the data handling further.
An alternate data preparation flow accommodating the larger files and re-gaining flexibility for turnaround time (TAT) and throughput management is suggested. This flow utilizes the hierarchical GDS-II format as the exchange format for mask data preparation. It complements the existing flow for the most complex designs. The introduction of a hierarchical exchange format enables the transfer of a number of necessary data preparation steps into the hierarchical domain. Data processing strategies are discussed. The paper illustrates the benefit of hierarchical processing based on GDS-II files with experimental data on file size reduction and TAT improvement for direct format conversions vs. re-fracturing as well as other processing steps. The implications for the established data preparation approaches and potential alternatives for the communication between the mask manufacturer and the customer will be discussed. The potential for further enhancements by converting to a hierarchical format that has a more efficient data representation than the commonly used GDS-II format will be discussed and illustrated.
Critical features of a product layout like isolated structures and complicated two-dimensional situations including line ends have often a smaller process window compared to regular highly nested features. It has been observed that the application of optical proximity corrections (OPC) can create yet more aggressive layout situations. Although corrected layouts meet the target contour under optimal exposure conditions, the process window of these structures under non-optimal conditions is thereby potentially reduced. This increases the risk of shorts and opens in the resist images of the designs under non-optimal exposure conditions. The requirement from a lithographer's point of view is to conduct a correction that considers the process window aspect besides the desired target contour. The present study investigates a concept of using the over-dose and under-dose responses of the simulated image of an exposed structure to optimize the correction value. The simulations describing the lithographic imaging process are based on an enhanced variable threshold model (VTRE). The placement error of the simulated edge of a structure is usually corrected for the nominal dose and focus settings. In the new concept the effective edge placement error is defined as the average of the edge placement errors for the over-dose and the edge placement error for the under-dose conditions. If a specific layout has a very non-symmetric response to over-/under exposure for the evaluated condition, it is prone to a certain failure mechanism (open or short). Hence calculating the average of the edge placement errors will shift the effective correction towards a layout with larger process window. The paper evaluates this concept for 100 nm ground rules and 193 nm lithography conditions. Examples of corrected layouts are presented together with experimental data. The limitations of the approach are discussed.
Sub-resolution assist features (SRAF) have been demonstrated to provide significant process window improvement when used in combination with off-axis illumination (OAI) and attenuated phase shifted mask enhanced lithography. While some through pitch linewidth variations can be reduced through the use of SRAF, the main goal is to improve common process window, leaving the task of linewidth control to conventional optical proximity correction (OPC). OPC in combination with SRAF is also required to address 2D patterning infidelities such as corner rounding and line end shortening, for which SRAF do not provide adequate correction. Finally, OPC will be used as a means of recovering process window that may be lost in layout situations that result in poor SRAF coverage. With an industry wide migration form rules-based OPC to iterative, model-based solutions, the integration of inherently rules based SRAF generation and model-based OPC has to be investigated.
RET treatments have become as integral a part of silicon manufacturing as steppers. For the 100-nm node, none of the critical layers can be adequately resolved without the application of at least one technique, and sometimes several in combination. All of these techniques can only be specified exactly in limited layout cases that are small enough for study and refinement. When the parameters defined in the initial study are applied to the full chip, however, the variability of real layout always leads to cases where the RET performs less than optimally. In fact, for most technqiues, the real layout imposes a balance between different layout needs. As an example, consider the use of off-axis illumination with sub-resolution assist features (SRAF). The illumination that performs ideally for the dense regions of the layout clearly does not work for all pitches thus the introduction of SRAF. Due to the limitations of infrastructure the SRAF assisted design is never an exact match to the dense reign the illumination is tuned for. The result is two-fold: one, the illumination must be relaxed in order not to be too selective of pitch, and the line width control across the chip becomes difficult. OPC and altPSM also both lead to the same two results when applied full chip.
In this paper, we present experimental results with a prototype design of a 'MEEF Meter,' and investigate its sensitivity to defocus and exposure changes. We find that the results of the MEEF meter complement the results obtained through conventional CD metrology, with conventional CDs being a good indicator of exposure changes, while the MEEF meter is a good indicator of defocus changes. We also investigate two kinds of MEEF meter, a dense MEEF meter and 'Process' MEEF meter design, and find the results for MEEF similar, but that the 'Process' MEEF meter design is far more susceptible to noise and bridging.
KEYWORDS: Optical proximity correction, Reticles, Manufacturing, Inspection, Photomasks, Semiconducting wafers, Data processing, Detection and tracking algorithms, Data modeling, Process modeling
As OPC becomes more widely used, there is great concern about additional time and costs that are incurred for both data manipulation and reticle manufacturing. In this paper, we discuss the optimal practices for the insertion of OPC into the standard IC pattern data generation, and find that the lowest risk point of insertion with the highest assurance of data integrity occurs when OPC is done as part of the physical verification process. In addition, we also examine the impact of OPC on reticle inspection practices, and find that, by following a few simple geometric guidelines, aggressive OPC can be implemented with no impact on reticle inspectability, significantly reducing the barriers to adoption.
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