Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from:
-Static RAM with very aggressive design rules specially at active, poly and contact
-transistor variability control at the chip level
The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm :
-dipole with polarization and regular layout for active level
-dipole with polarization, regular layout and double patterning to cut the line-end for poly level.
These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.
Line-end pullback has been an issue for photoresist patterning for many years. The two-dimensional nature of line-ends leads to increased deprotection of the resist and shortening of the resist features. From a lithographic standpoint, line-end pullback can be mitigated to some extent using optical proximity correction (OPC). However, as the space between line-ends gets smaller, a trade-off exists with respect to OPC. Over-correction of the line-end on the reticle by the addition of hammerheads can lead to bridging. In some cases, the line-end spacing can actually be less than design rules. The poor aerial image contrast at these line-ends can lead to sloped profiles as well as pullback. The line-end slope depends on the resist contrast, the OPC, and the target line end-to-end space. These sloped line ends lead to increased pullback during the subsequent gate etch process. For gate patterning, a resist trim step is often utilized prior to etching a hardmask and polysilicon. During each etch step the resist line-end is quickly eroded due to the sloped profile. In this paper, we present a novel post-develop processing technique for improving the line-end profile of patterned photoresist. This improvement in the line-end profile results in less pullback during subsequent etch processing. After development, a patterned photoresist film is treated to a gas phase fluorination process. The fluorination process leads to substitution of F for H in the polymer matrix of the resist film, and causes the resist to swell. This swelling causes the line-end profile to become more vertical due to the fact that the base of resist features are anchored to the substrate, and only the top portion of the resist features will swell. This improvement in the line-end profile is shown to reduce line end-to-end spacing by 20-30% after etch. Cross-sectional images show the improvement throughout the partitioned etch process. Simulation results verify that a more vertical line-end slope is sufficient to decrease line-end pullback during etch.
As semiconductor gate lengths shrink, photoresist trends toward thinner films. Thick photoresist films are not desirable because they tend to absorb more light, require higher energies to pattern, increase pattern collapse, and subtract from depth of focus and exposure latitude. The minimum thickness of implant photoresist is governed by the stopping power of the photoresist for the ion type and the energy of the implant. Relatively high energy implants and/or lower ion stopping power in the photoresist require thicker photoresist films. These problems can be mitigated through a novel photoresist fluorination process. The fluorination process results in the replacement of H atoms by heavier F atoms effectively increasing the molecular weight of the fluorinated film and its ability to block ion implantation. This straightforward and cost-effective process is investigated for use with a standard 248 nm dyed photoresist. Substrate damage probe measurements and Secondary Ion Mass Spectrometry depth profiles show species-dependent ion implant masking improvements of up to 40 % for fluorinated photoresist versus as-developed photoresist. Geometric and process margin arguments are discussed for thinning photoresist where angled implants are needed or process capability is insufficient. Finally, electrical data is presented that demonstrates the manufacturability of these fluorinated and thinned photoresist films.
Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm1. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.
Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm-1. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.
The minimum gate pitch for the 65 nm device node will push 193 nm lithography toward k1~0.35 with numerical aperture (NA)=0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65 nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift masks (high-T attPSMs), where T>14%, to improve process margins. The benefits of a high-T attPSM are substantial, but drawbacks like difficulty in inspection, defect free blank manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65 nm node with 193 nm lithography. Earlier work has shown that the problems high-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75 NA 193 nm wavelength results for 6% versus 9% attPSM on the gate, contact/via, and metal layers at 65 nm generation target dimensions with leading edge resists.
The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift mask (high-T attPSM), where T > 14%, to improve process margins. The benefits of a high-t attPSM are substantial, but drawbacks like inspection difficulty, defect free blanks manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65nm node with 193nm lithography. Earlier work shows that the problems High-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75NA 193nm λ results for 6% versus 9% attPSM on gate, contact/via, and metal layers at 65nm generation target dimensions with leading edge resists. Additional information on the inspectability and reticle blank manufacture of % AttPSM will also be given to provide a cohesive analysis of the transition tradeoffs.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k1 regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k1 range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k1, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.
Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.
Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.
Complementary phase shift mask (c:PSM) is one of the most promising resolution enhancement techniques (RET) to extend low k1 optical lithography. Nonetheless binary intensity mask (BIM) imaged with 193 nm wavelength at high numerical aperture (0.75) off-axis illumination (OAI) might still be used for nested through isolated feature sizes as small as 70 nm. We compare the feasibility of using c:PSM and BIM for 70nm generation technologies. Experimental results of high NA imaged BIM and c:PSM are presented.