Analog optical fronthaul for 5G network architectures is currently being promoted as a bandwidth- and energy-efficient technology that can sustain the data-rate, latency and energy requirements of the emerging 5G era. This paper deals with a new optical fronthaul architecture that can effectively synergize optical transceiver, optical add/drop multiplexer and optical beamforming integrated photonics towards a DSP-assisted analog fronthaul for seamless and medium-transparent 5G small-cell networks. Its main application targets include dense and Hot-Spot Area networks, promoting the deployment of mmWave massive MIMO Remote Radio Heads (RRHs) that can offer wireless data-rates ranging from 25Gbps up to 400Gbps depending on the fronthaul technology employed. Small-cell access and resource allocation is ensured via a Medium-Transparent (MT-) MAC protocol that enables the transparent communication between the Central Office and the wireless end-users or the lamp-posts via roof-top-located V-band massive MIMO RRHs. The MTMAC is analysed in detail with simulation and analytical theoretical results being in good agreement and confirming its credentials to satisfy 5G network latency requirements by guaranteeing latency values lower than 1 ms for small- to midload conditions. Its extension towards supporting optical beamforming capabilities and mmWave massive MIMO antennas is discussed, while its performance is analysed for different fiber fronthaul link lengths and different optical channel capacities. Finally, different physical layer network architectures supporting the MT-MAC scheme are presented and adapted to different 5G use case scenarios, starting from PON-overlaid fronthaul solutions and gradually moving through Spatial Division Multiplexing up to Wavelength Division Multiplexing transport as the user density increases.
Content Addressable Memories (CAMs) are widely used in nowadays router applications due to their fast bit searching capabilities. However, address loop-up operation cannot still keep up with high data-rate speeds of optical packet payload due to the limited speeds offered by electronic technology, which hardly can reach a few GHz. Despite this limitation, optics has still not managed to penetrate in the area of address look-up and forwarding operations due to the complete lack of optical CAM-based solutions. To the best of our knowledge, the first all-optical binary CAM cell has been only recently experimentally demonstrated by our group using an all-optical monolithically integrated InP Flip-Flop and an optical XOR gate, revealing error-free operation at 10 Gbps for both Content Addressing and Content Writing operations. In this paper, we extend our previous work by presenting for the first time to our knowledge an all-optical Ternary CAM cell architecture that allows also for a third matching state of "X" or "don’t care", thus adding the necessary searching flexibility required by modern CAM-based solutions for supporting subnet-masked addresses. Moreover, we exploit the optical Ternary CAM cell towards deploying a complete CAM row formed by 4 Ternary CAM cells, demonstrating its operation through VPI simulations at 10 Gbps for an indicative 2 bit packet address and for both Content Addressing and Content Writing functionalities. The potential of this memory architecture to allow for up to 40 Gbps operation could presumably lead to fast CAM-based routing applications by enabling all-optical Address Lookup schemes.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.