A novel 2-bit optical-input optical-output analog-to-digital converter (ADC) is demonstrated in self electro-optic device (SEED)
technology using a threshold logic technique. The threshold gate was
constructed using a resistor-SEED (R-SEED) which is composed of a large value resistor and a SEED area of 500 um x 500 um. Each gate operates as a majority function that has a threshold level controlled by a fixed optical input. The ADC was constructed using two R-SEED gates operating at wavelength of 846 nm. The test bench set-up operates at 100 Hz. However, as the proposed architecture is scalable, it can operate at much higher speeds and generate larger number of bits. This architecture is only limited by the switching speed of the SEED and propagation delay through each threshold gate.
This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor level
delay estimation. The adder is a hybrid design, consisting of domino
logic and the recently proposed Charge Recycling Threshold Logic
(CRTL). The delay evaluation is based LE modeling of the delay of
the domino and CRTL gates. From the initial estimations, the 8-bit
sparse carry look-ahead/carry-select scheme has a delay of less than
5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 FO4
delay faster than any previously published domino design.
In recent years, there has been renewed interest in Threshold Logic
(TL), mainly as a result of the development of a number of
successful implementations of TL gates in CMOS. This paper presents
a summary of the recent developments in TL circuit design.
High-performance TL gate circuit implementations are compared, and a
number of their applications in computer arithmetic operations are
reviewed. It is shown that the application of TL in computer
arithmetic circuit design can yield designs with significantly
reduced transistor count and area while at the same time reducing
circuit delay and power dissipation when compared to conventional
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.
The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.
The main result of this paper is the development of a systematic
paper-and-pencil design methodology for implementing Boolean
functions of up to 4 variables using threshold logic (TL) gates, which
does not require linear programming, for the first time. The method
is similar in operation to the Karnaugh map logic minimization
technique, and is based on determining the minimum threshold cover
of a Boolean function. The paper also reviews aspects of TL and
discusses aspects of the proposed design methodology when combined
with the implementation issues present in neuron-MOS based TL gates.
Two circuit design examples using the proposed technique are given.
The neu-MOS transistor, recently discovered by Shibata and Ohmi in 1991, uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, ie. at the most elemental level in circuits, introduces a degree of flexibility which may lead to the realization of intelligent functions at a system level. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count, area and power dissipation reduction through the use of neu-GaAs in VLSI design. Due to the proprietary nature of complementary GaAs data and SPICE parameters, the simulation result are based on a representative composite parameter set derived from a number of complementary GaAs processes. Preliminary simulations indicate a factor of 4 reduction in gate count, and a factor of over 50 in power dissipation over conventional complementary GaAs. Small gate leakage is shown to be useful in eliminating unwanted charge buildup on the floating gate.