The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.
We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILETM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILETM, which validated our method and shows the possibilities of AGILETM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.
We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.
In this paper we performed an analysis of various data collection preformed on C045 production lots in order to
assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to
show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners
combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers.
After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process
windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible,
in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to
achieve a better global CD uniformity.
The lithography prognosticator of the early 1980's declared the end of optics for sub-0.5&mgr;m imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several author have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges.
Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k1 imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.
Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from:
-Static RAM with very aggressive design rules specially at active, poly and contact
-transistor variability control at the chip level
-random layouts
The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm :
-dipole with polarization and regular layout for active level
-dipole with polarization, regular layout and double patterning to cut the line-end for poly level.
These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.
To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers are on their way to introduce the alternating phase shift mask (APSM) to be able to print the gate level on sub-130-nm devices. This is done at very high mask costs, long cycle times, and poor guarantees to get defect-free masks. Nakao et al. have proposed a new resolution enhancement technique (RET). They have shown that sub-0.1-µm features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension of this technique called complementary double exposure (CODE). It combines Nakao's technique and the use of assist features that are removed during a second subsequent exposure. This new method enables us to print isolated as well as dense features on advanced devices using two binary masks. We describe all the steps required to develop the CODE application. The layout rules generation and the impact of the second mask on the process latitude have been studied. Experimental verification has been done using 193-nm 0.63 and 0.75 numerical aperture (NA) scanners. The improvement brought by quadrupole or annular illuminations combined with CODE has also been evaluated. Finally, the results of the CODE technique, applied to a portion of a real circuit using all the developed rules, are shown.
In a previous paper, we have proposed the CODE (Complementary Double Exposure) technique. A new manufacturable Reticle Enhancement Technique (RET) using two binary masks. We have demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using the CODE technique and showed good printing results using a 0.63NA ArF scanner. In a more recent article we described all the steps required to develop the CODE application: the binary decomposition and the solutions developed in order to compensate adequately for line end shortening. This study was done based on aerial image simulations only. In this paper, we will give experimental results for printing complex two-dimensional structures for the high performance version of a 90nm ground rule, 240nm minimal pitch process, using the CODE technique. The results of depth of focus (DOF), energy latitude (EL) and mask error enhancement factor (MEEF) through pitch, and end-cap correction will be discussed, for quadrupole and annular illumination using a 193nm 0.70NA exposure tool. The CODE technique, not only because of a lower cost but also because of its performance, could be a good alternative to the alternating PSM technique, having less design penalties and a better mask making cycle time.
xIn order to address some specific issues related to gate level printing of the 0.09μm logic process, the following mask and illumination solutions have been evaluated. Annular and Quasar illumination using binary mask with assist feature and the CODE (Complementary Double Exposure) technique. Two different linewidths have been targeted after lithography: 100nm and 80nm respectively for lowpower and high-speed applications. The different solutions have been compared for their printing performance through pitch for Energy Latitude, Depth of Focus and Mask Error Enhancement Factor. The assist bar printability and line-end control was also determined. For printing the 100nm target, all tested options can be used, with a preference for Quasar illumination for the gain in Depth of Focus and
MEEF. For the 80nm target however, only the CODE technique with Quasar give sufficient good results for the critical litho parameters.
In a recent paper, we proposed a new manufacturable Reticule Enhancement Technique (RET) using two binary masks, called CODE (Complementary Double Exposure). We demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using this technique and showed good performance using an ArF 0.63NA scanner. To be able to use the CODE RET in production, we must be able to handle complex two-dimensional structures as well. In this paper we study the representative two-dimensional complex structures of a circuit in order to have a complete overview of this technique. We analyze the impact of the asymmetrical apertures and the impact of the 2nd mask overlap to the 1st mask. We show that asymmetrical apertures impact the line width of the non-critical lines. We also show that the 2nd mask has not only the role of protecting the exposed part. It also contributes strongly to the printability of the complex structures by correcting the defects of the 1st exposure. Finally, we show the results of CODE technique applied to a portion of a real circuit using all the developed rules.
Quality of exposures on Step&Scan systems highly depends on stages synchronization. While scanning, wafer and reticle stages must have same relative speed (4x ratio) and directions. In this paper, we investigate the tolerance to lateral vibrations of 0.18micrometers and 0.12micrometers gate patterning respectively on an ASML PAS5500/750E scanner (KrF) and a PAS5500/900 scanner (ArF) exposure tools. Results should be given both on the MA impact on overlay and the MSD effect on CD control. But, as no adapted experimental method has been found to correlate overlay degradation to induced MA and then confirm the theory that 1nm of MA induces 1nm of translation, only results on CD control will be discussed, including lateral MSD impact on nominal CD variations, process latitudes degradations and intrafield CD dispersion. In particular, we will show that MSD effect on CD strongly differs from 248nm imaging process to 193nm one.
The insertion point for the first scattering bar is a key point in the development of a process using assist features, because this semi dense feature will determine the overall depth of focus of the process. A study of the parameters, which influence the choice of this insertion point, has been performed using a 0.63 NA 193 nm scanner for a 100 nm CD target after litho. The impact of the scattering bar on: Depth of Focus, Energy Latitude, Mask Error Enhancement Factor, printability, and the effect of scattering bar line width variation on main feature described by a parameter called AFMEEF will be discussed in this paper. The optimal insertion point for the first scattering bar will strongly depend on the litho-graphic process and the mask parameters. A model is proposed to determine the optimal insertion point, as function of the dose, focus budget, minimal allowed scatterbar width, and mask CD dispersion for both scattering bars and main features.
To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakao's technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.