The practical boundaries surrounding the design of very high resolution image sensors have been studied. The case study used to analyze these practical boundaries is a CMOS photodiode active pixel sensor (APS) image sensor with pixel array format of 3,072 (H) X 2,048 (V). The frame rate of the image sensor is variable up to 30 frames per second (fps), leading to a maximum image data throughput of 180 M pixels per second. The pixel size is 6.0 μm, resulting in a pixel fill factor of approximately 48% (implemented in a 0.25 μm CMOS fabrication process) and a 4/3 inch optical format. The resultant die fill factor is approximately 54%. The column-parallel approach, which works well for both the on-chip analog signal processing and analog-to-digital conversion, is adopted. The 10-bit successive approximation ADC was deemed suitable for on-chip integration. The projected total power consumption of the case study image sensor chip is below 200 mW at 3.3-V power supply and below 100 mW at 1.5-V power supply. These power estimates were made for operation at full resolution (6 M pixels per frame) and at maximum frame rate (30 fps), leading to a maximum digital image data throughput of 1.8 G bits per second.
A CMOS APS Image sensor test chip was designed employing the physical design techniques of enclosed geometry and guard ring, and according to the design rules of a 0.35-micrometers CMOS standard process that has a gate oxide thickness of approximately 7.0 nm. Three sets of radiation tolerant photodiode active pixels were developed employing these design techniques. They are N-type, and H-type pixels. Each of the pixels is a square pixel with a 16.2 micrometers pitch. The yielded fill-factor is approximately 50 percent. Depending on the pixel-type and the layout, the simulated output voltage swing ranges from 300 mV to 1.1 V. The peripheral circuits, which include decoders, row/column drivers, and I/O pads, were also developed. All NMOS transistors in the peripheral circuits were laid out employing the physical design techniques of enclosed geometry and P-type guard ring. Integrating the pixels and the peripheral circuits into the design of radiation hard CMOS APS image sensor has bene completed. The size of the pixel array is 256 by 256, constituting an imaging area of approximately 4.1 mm X 4.1 mm. The total size of the die is approximately 5.2 mm X 5.0 mm. The total number of the I/O pads is 42. Plans to irradiate these image sensor using Cobalt-60 to determine the level of their radiation hardness are currently being devised.
A CMOS APS image sensor test chip, which was designed employing the physical design techniques of enclosed geometry and guard rings and fabricated in a 0.5-micrometers CMOS process, underwent a Co60 (gamma) -ray irradiation experiment. The experiment demonstrated that implementing the physical design techniques of enclosed geometry and guard rings in CMOS APS image sensors is possible. It verified that employing these design techniques does not represent a fundamental impediment for the functionality and performance of CMOS APS image sensors. It further proved that CMOS APS image sensors that employ these physical design techniques yield better dark signal performance in ionizing radiation environment than their counterpart that do not employ those physical design techniques. For one of the different pixel designs that were included in the test chip pixel array, the pre- radiation average dark signal was approximately 1.92 mV/s. At the highest total ionizing radiation dose level used in the experiment (approximately 88 Krad(Si)), average dark signal increased to approximately 36.35 mV/s. After annealing for 168 hours at 100 degree(s)C, it dropped to approximately 3.87 mV/s.
In this paper, a new CID image sensor architecture, pre-amplifier per pixel (PPP), is presented. In this architecture, an amplifier is dedicated to and integrated within each pixel of the image sensor array. The read-out node for a pixel design employing this architecture is local to its pixel and buffered from any other read-out nodes within the image sensor pixel array. Thus, the capacitance of the read-out node in this design is significantly reduced, resulting in significant improvements of read-out sensitivity and noise. This architecture reduces the read-out node capacitance to an order of magnitude of few tens of fF, which yields an rms read-out noise in the order of few tens of electrons. This brings the CID imaging technology to the main stream of read-out noise levels of other solid-state imaging technologies. This is achieved without compromising the traditional strengths of CID imaging technology such as non-destructive read-out, resistance to blooming, radiation hardness, and random-accessibility. The only compromise is the pixel fill-factor. Depending on the minimum process feature size and the pixel size, the pixel fill-factor can be higher than 50%. A test chip has been designed and fabricated. Evaluation of this test chip is presented.
A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.
The performance of a large format (512 X 512, 20.3 mm diagonal) Charge Injection Device (CID) imager which was fabricated for use in spectroscopy, microscopy and other scientific instrumentation applications is reported herein. The device incorporates a large (28 X 28 micron) pixel size and on-chip signal amplification to achieve large full well capacity, low noise and wide dynamic range. As do other CIDs', the device also features a broad spectral response, virtually no blooming, true Non-Destructive Signal Read-Out (NDRO), video skimming and individual pixel address capability. Together, these unique CID features provide the capability to extend the imager dynamic range, achieve real-time signal monitoring and read-out for adaptive exposure control, and achieve lower noise through NDRO signal averaging.
A new large format (512 X 512) charge injection device (CU)) imager was designed and fabricated for use in spectroscopy and other scientific instrumentation applications. Because of its large pixel size (28 urn X 28 urn) the imager design features wide dynamic range and extended spectral response. Additionally a pre-amplifier per row read-out architecture is employed to reduce read-out noise by an order of magnitude from that of a conventional read-out architecture. Initially the imager was fabricated using a commercial oxide-nitride CD process. Eventually an all-oxide CD process will be employed to fabricate the imager. The removal of the nitride is projected to reduce further the read-out noise as well as optimize the UV response. The imager is being integrated in an existing CPU-based scientific instrumentation camera. Among the features that will be demonstrated are: wide dynamic range low read-out noise improved spectral response virtually no-blooming random-access capability true non-destructive read-out and adaptive integration time. 1.
An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2 of the total chip area and is performed using three parallel-serial-parallel (SP3) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP3 architecture, at an output rate of 83 X 103 pixels/sec. (0.9996 at 2 X 106 pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.
A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The simulation of an edge detection algorithm implemented by the chip is presented. An overview of the chip performance is described as well.
The design of a CCD image half-toner integrated monolithically on the focal plane with a 256 x 256 frame transfer imager is reported and the algorithm used is discussed. The imager/half-toner chip is projected to achieve a throughput of 30 frames per second.
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