In the past decade, Field Programmable Gate Arrays (FPGA) has significantly influenced the landscape of the electronic industry. In particular, in the areas of semiconductor manufacturing, CAD tool designs and a wide range of digital logic applications. Primarily, research efforts in the FPGA community have concentrated on improving the reconfigurability or programmability of present day architecture for digital applications. However, the digital nature of FPGA technologies limits their applicability to a wide range of applications that depend on analog circuitry, photonic and RF based technologies. As with any ASIC design, the turn-around time between design iterations may be several months which is prohibitively long for multi-technology test-bed systems where the system designer depends on a rapid prototyping/experimentation environment that allows for optimization of processing algorithms and system architecture. Therefore, we developed innovative FPGA architecture that merges conventional FPGA technology with mixed signal and other multi-technology device. In this paper we discuss the Multi-Technology-FPGA (MT-FPGA) architecture that allows the user to have flexible rapid prototyping environment and provides him or her with the benefits of a conventional FPGA in a mixed signal domain. We substantiate this concept by implementing this architecture in TSMC 0.35 μm process and discussing the results of a variable threshold optical receiver circuit suitable for photonic information processing.
Recent advances in the integrated electronic circuit industry have spurred efforts to develop technologies that efficiently integrate optics and electronics on a single Complementary Metal Oxide Semiconductor (CMOS) chip. Such CMOS technologies can significantly increase circuit functionality and performance at low fabrication and system cost, thereby accelerating the trend of significant growth in this area. The new functionality could include optical based sensors, image processing, and intelligent optical read heads for faster and more efficient data sorting and searching. The reliability of such monolithic CMOS based functions would be drastically improved relative to their bulk optic counterparts. In the optical telecommunications industry, short haul fiber links would benefit from low cost, silicon CMOS based photoreceivers. One of the primary challenges facing the designers in implementing CMOS based optoelectronic circuits is opto-electrical conversion efficiency. The poor optical responsivity of silicon leads to a bottleneck in the optical to electrical conversion for CMOS based photodetectors. This can be compensated in part through more efficient receiver electronics. Efforts have been made to provide mixed signal circuit design to analyze CMOS based high performance, low noise, integrated receiver circuits. This paper evaluates the performance analysis of five types of photoreceiver configurations that were designed for specific applications.
Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA’s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.
KEYWORDS: Data processing, Data storage, Logic, Data communications, Computer architecture, Optical communications, Photonic devices, Very large scale integration, Photodetectors, Spatial light modulators
The ever-increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics devices and conventional data processing circuitry. Based on the smart-pixel architectures first developed in the last decade, the architecture presented here monolithically integrates optical sensors with silicon CMOS-based circuitry to produce a generically programmable smart-pixel array. Two generations of the architecture are described and compared. We have proposed a reconfigurable photonic information-processing chip based on photonic VLSI device technology. Integrating detectors into a SIMD array removes the bottleneck associated with fetching slices of data. By fabricating the detectors along with logic circuits in a bulk CMOS process, the cost is minimized. The modular nature of the array organization facilitates replication of the configurable architecture for smart-pixel research (CASPR) concept into large arrays without a significant increase in design overhead. Thus, the CASPR architecture can provide the maximum flexibility associated with a reconfigurable smart-pixel array. Finally, we implement two design iterations of the CASPR architecture and show how the architecture might be used in a page-oriented optical data processing application.
KEYWORDS: Field programmable gate arrays, Switches, Logic, Multiplexers, Analog electronics, Data processing, Digital electronics, Oscillators, Very large scale integration, Clocks
We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.
A new multi-technology FPGA (MT-FPGA) architecture has recently been proposed. This new class of programmable hardware allows for the incorporation of a variety of multi-technology blocks like the optical sensor block as described in this paper. Using MT-FPGA technology, a system designer can readily implement any prototype multi-technology system with (1) logic parts in programmable section of MT-FPGA and (2) Multi-technology components by incorporating different multi-technology blocks from standard library. Thus, our new class of multi-technology FPGA will extend the benefits of rapid prototyping, re-configurability and evolvable hardware to multi-technology environments/applications that currently do not benefit from the advantages of programmable hardware. This paper highlights the use of an MT-FPGA chip through the implementation and evaluation of an optical power meter block. This mixed technology block is designed for implementation using a 0.35 micron CMOS process and consists of a p-diffusion to n-well photodetector followed by a wide-swing variable gain differential amplifier and a 4 bit FLASH ADC. The amplifier gain characteristics are adjustable by two analog control signals. One adjusts the gain and the other controls the biasing conditions of the differential amplifier. The last stage of the system is a 4 bit ADC that has a worst case resolution of 0.5 mV.
KEYWORDS: Field programmable gate arrays, Analog electronics, Sensors, Optical amplifiers, Very large scale integration, Transistors, Data processing, Logic, Semiconductor lasers, Digital electronics
We present her a user programmable photoreceiver block that is monolithically integrated in a new generation of multi-technology field programmable gate array (MT-FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We also report here on the photoreceiver design methodology in a mixed signal environment and simulation results indicating the device performance.
KEYWORDS: Data processing, Very large scale integration, Data storage, Photonic devices, Logic, Data communications, Computer architecture, CMOS technology, Optical storage, Prototyping
The design, demonstration and evaluation of a general purpose, smart pixel based photonic information processing unit is presented. Based on a photonic VLSI device technology that can be implemented using a standard 1.5-micrometers CMOS, each pixel incorporates a photoreceiver with a RISC processor and produces a device that is suitable for prototyping photonic information processing systems.
The design, demonstration and evaluation of a general purpose, field programmable smart pixel based photonic information processing system is presented. This novel architecture incorporates photoreceiver cells into a field programmable gate array (FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We report here on the photoreceiver design methodology and measure device performance.
The design, demonstration and evaluation of a general purpose, field programmable smart pixel based photonic information processing system is presented. This novel architecture incorporates programmable photoreceiver cells into a field programmable gate array (FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We report here on the programmable photoreceiver design methodology and measure device performance.
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