The efficacy of currently available repair techniques has been assessed for a wide variety of defect types encountered on advanced lithographic masks. Focused ion beam (FIB) with gas-assisted etching and deposition, electron beam induced chemical processing (EBIC), and atomic force microscope based nano-machining (RAVE) were among the different methodologies evaluated. Various types of optical phase-shifting masks for the 45nm lithographic node, as well as nano-imprint lithography (NIL) templates, were used as test vehicles. Defect imaging resolution, spatial process confinement, repair edge placement, end-pointing control, sample damage (undesired changes in topographic or optical properties), and future extendibility served as the primary metrics for gauging repair performance. The primary aim of this study was to provide a single "snapshot" in time of the current development status of each tool for the context of 45nm node mask repair specifications and by no means were there any expectations for a final solution to already be commercially available. However, the results obtained from these tests should provide useful feedback and information to help improve the learning cycle for the development of 45nm lithographic node mask repair systems.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology also. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications. The advantages on the wafer side for the adoption of imprint lithography is the simplification of processing, reduced capital costs and process control when integrated in the wafer fab. The adoption of imprint reduces the barrier of entry to state of the art resolution for many older existing fabs that cannot spend upwards of 30 million dollars on an immersion I-line cluster. In this paper we will explore not only the technical aspects of imprint lithography, but also the economic impact as well.
Photomasks to support 45nm node circuit development will be needed by mid year 2007 to meet the most aggressive device development programs. Volume manufacturing of 45nm technology photomask, however, would not occur until 2-3 years later. Either case would require an advanced photomask lithography capability that can meet the 45nm node specifications. From a mask maker's perspective, a lithography tool platform that is flexible, that supports high resolution and can be ramped for throughput would be the best solution. In an effort to understand if a potential tool platform(s) will exist, Photronics performed characterization and assessment studies of all commercial mask pattern generator platforms. All mask pattern generator tools, including both e-beam and laser platforms, were evaluated for performance against 45nm node target specifications as defined by the International Technology Roadmap for Semiconductors.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology. MEMS devices that can be scaled to smaller dimensions, construction of nano-optical devices for OLED applications, biosensors, light dispersion gratings and many other types of devices in need of nanometer scale fabrication. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications.
Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs.
In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance.
We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.
To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.
Minimizing mask-level distortions is critical to ensuring the success of electron projection lithography (EPL) in the sub-65-nm regime. Previous research has demonstrated the importance of controlling the stress in the patterned stencil membranes to minimize image placement distortions. Low-stress, 100-mm diameter EPL mask blanks have been patterned with a layout that simulates the effects of the cross-mask and intra-subfield pattern density gradients found in a realistic circuit design. Extensive IP measurements were made to illustrate how local subfield correction schemes can be used to reduce all mask-level distortions (regardless of pattern type) to less than 15 nm (3s). Combining membrane stress control with the use of repeatable and identical reticle chucking is expected to reduce EPL mask-level distortions to the values that will be needed for the 65-nm design node.
The future of mask industry technology is in flux. While the requirements for current and near-term lithographic capability is well understood, advanced lithography options pose a completely new set of challenges to the mask maker. Challenges are not only process and materials related, but also include more fundamental concerns dealing with how to afford the necessary capability development. This paper identifies the issues and attempts to propose solutions to the industry's growing concerns.
Minimizing mask-level distortions is critical to the success of electron projection lithography (EPL) in the sub-100-nm regime. A number of possibilities exist to reduce mask-fabrication and pattern-transfer distortion including subfield correction, "dummy" patterns, pattern splitting, and film stress control. Finite element modeling was used to illustrate the advantages and capabilities of these correction schemes for a 100-mm stencil mask with 1-mm×1-mm membrane windows. Static-random-access-memory-type circuit features, including both the interconnect and contact levels, were used, to simulate realistic circuit layouts with both cross-mask and intra-membrane pattern density gradients. With such correction techniques, it is possible to reduce the EPL mask-level distortions for "worst-case" mixed pattern types to less than 1.0 nm.
International SEMATECH (ISMT) established a program in 1996 to narrow the Next Generation Lithography (NGL) options on the SIA Roadmap through a global consensus process. Methodologies developed by the SIA Lithography Technical Working Group (TWG) were adopted to ensure a balanced and objective assessment. Critical reviews with emphasis on technical program plans, solutions to critical issues (showstoppers), error budget analysis, cost-of-ownership, business plans, and schedules were implemented with the Technical Champions of each technology. White papers were written by the Technical Champion teams to better educate the participants in the annual worldwide NGL workshops. Participants made their recommendations through a survey conducted at the end of each workshop. A Task Force of the key stakeholders from global chip makers, equipment suppliers and consortia was commissioned to review the workshop output, assess the progress on the critical issues and make recommendations to ISMT on narrowing the options. As a result of this global consensus process and the critical issue projects, the NGL Task Force has made the following recommendations: (i) November 1997 - Massively Parallel Direct Write (MPDW) is not mature enough for introduction until at least the 50nm node. (ii) December 1998 - ISMT should narrow its support to two options EUVL and EPL, and that other worldwide activity on X-Ray and IPL continue. (iii) December 1999 - ISMT should continue its support for EUVL and EPL for the 70nm node, it also recognized the growing possibility that the industry might need more than one mainstream technology for the diverging application of DRAM/MPU and ASIC/SOC. (iv) September 2000 - The industry in general should narrow its support for commercialization to EUVL and EPL for insertion at the 70nm node. (v) August 2001 - The industry should continue to fund the commercialization of both EUVL and EPL. Today, the ISMT program for NGL is transitioning from option selection to promoting critical issues solutions and commercial infrastructure for EUVL with initial focus on mask blanks. ISMT is also pursuing collaboration with the suppliers and consortia developing EPL technology to provide stable stencil mask for contact layers. This paper describes the evolution of the program, results of the year 2001 activities, and the plans for 2002.
Minimizing mask-level distortions is critical to the success of Electron Projection Lithography (EPL) in the sub-100 nm regime. A number of possibilities exist to reduce mask fabrication and pattern transfer distortion including subfield correction, 'dummy' patterns, pattern splitting and film stress control. Finite element modeling was used to illustrate the advantages and capabilities of these correction schemes for a 100-mm stencil mask with 1 mm X 1 mm membrane windows. SRAM-type circuit features including both the interconnect and contact levels were used to simulate realistic circuit layouts with both cross-mask and intra-membrane pattern density gradients. With such correction techniques, it is possible to reduce the EPL mask-level distortions for 'worst-case' mixed pattern types to less than 1.0 nm.
As optical lithography error budgets on pattern placement become more and more stringent for sub-130 nm technology, all mask-related distortions must be quantified, controlled, and minimized. To optimize the mask fabrication process, it is essential to identify the stress magnitudes of the thin films and determine the resulting effect on pattern placement errors. Experiments utilizing surface mapping technique have been used to quantify the stress magnitudes of current thin film deposition parameters used in photomask blank fabrication. The effect of pattern transfer on image placement errors was determined experimentally for an anisotropic metrology pattern. The stress magnitudes obtained in the thin film stress measurements were incorporated into a finite element model that simulated the mechanical effect of pattern transfer utilizing equivalent modeling techniques. Analytical, experimental, and finite element procedures have been integrated to accurately quantify thin film stress magnitudes and the corresponding pattern transfer distortions.
By operating at wavelength near 10-20 nm, EUV lithography can allow for imaging below 100 nm with limited diffractive losses. The reflective optics involved in such systems require multilayer coatings with stringent demands on throughput, uniformity, and stability. The performance of such multilayers is dependent on the optical properties leading to multilayer stacks requiring up to 40 layer pairs. An exhaustive study of potential material combinations has been performed. Detailed results from the investigation of candidate EUV reflective multilayers is presented. Beryllium and silicon are unique in the 10 to 20 nm wavelength range as materials with high index values and suitably low absorption. The best performing coatings within this range are therefore combinations of these two materials with low absorbing low index films, including many refractory metals. For each multilayer coating type investigated, the wavelength of maximum reflectivity has been optimized, and stress, thickness variation, scattering, and interfacial layer formation effects have been characterized.