Mr. Rene M. Blanquies Profile

Rene M. Blanquies

Research and Development Engineer at VLSI Standards Inc

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Publications (4)

Proceedings Article | 24 May 2004 Paper

Sub-50-nm isolated line and trench width artifacts for CD metrology

Marco Tortonese, Gian Lorusso, Rene Blanquies, Jerry Prochazka, Luca Grella

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536812

KEYWORDS: Silicon, Oxides, Semiconducting wafers, Transmission electron microscopy, Line edge roughness, Polishing, Critical dimension metrology, Etching, Calibration, Line width roughness

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Proceedings Article | 2 June 2000 Paper

Predictive process control for sub-0.2-um lithography

Terrence Zavecz, Rene Blanquies

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386497

KEYWORDS: Data modeling, Overlay metrology, Reticles, Error analysis, Semiconducting wafers, Process control, Metrology, Optical alignment, Lithography, Databases

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An advanced control system providing modeling and predictive data simulation for pass-fail criteria of overlay production control has been used in 0.18 micrometer Design Rule production facilities for over a year. During this period overlay was measured on both product wafers and during periodic process qualification tests. The resulting raw data is modeled using exposure tool specific and layer-focused models. Modeled results, measured process statistics and tool signatures are combined in a real-time simulation to calculate the true overlay distribution over the entire wafer and lot. All results and raw data are automatically gathered and stored in a database for on-going analysis. In this manner, tool, product technology and process performance data are gathered for every overlay process-step. The data provides valuable insights into not only tool stability but also the process- step characteristic errors that contribute to the overlay spectrum of distortions. Data gathered in this manner is very stable and can be used to predict a feed-forward correction for all correctable coefficients. The technique must take into consideration algorithm modeled coefficient variations resulting from: (1) Reticle pattern-to-alignment mark design errors. (2) Process film variations. (3) Tool-to-tool static matching. (4) Tool-to-tool dynamic matching errors which are match-residual, process or time induced. This extensive database has resulted in a method of conducting Predictive Process Control (PPC) for overlay lithography within an advanced semiconductor line. Using PPC the wafer production facility experiences: (1) Improved Yield: Lots are always exposed with optimum setup. Optimized setups reduce rework levels and therefore wafer handling. (2) Capacity Improvement: Elimination of rework tacitly improves capacity in the facility. WIP is also simplified because lots do not have to wait for a dedicated exposure tool to become available. (3) Dynamic Matching^TM: Matching of multiple exposure tools is continuously monitored by the use of the feedback loop. Tool precision can be monitored as well as the setup systematic offsets. In this manner, the need to remove an exposure tool from production for match-maintenance can be predicted and scheduled. Residual matching errors can also be removed from the production cycle. The benefits of full production lot modeling and the contributors to production errors are presented. Process and Tool interactions as well as control- factor coefficient stability indicate the level of control to be well beyond manual methods. Calculations show that these contributors are predictable, stable and are a necessary tool for competitive sub-0.2 micron production. An analysis of the overlay error sources within two facilities results in consistent facility process response and a well-defined error budget derivation. From this analysis, the control added to semiconductor overlay is shown capable of extending mix-and- match exposure tool operations in production down to 0.12 micrometer design rules.

Proceedings Article | 3 February 2000 Paper

Reticle programmed defect size measurement using low-voltage SEM and pattern recognition techniques

Larry Zurbrick, Steve Khanna, Jay Lee, James Greed, Ellen Laird, Rene Blanquies

Proceedings Volume 3996, (2000) https://doi.org/10.1117/12.377119

KEYWORDS: Scanning electron microscopy, Optical testing, LCDs, Reticles, Pattern recognition, Photomasks, Critical dimension metrology, Very large scale integration, Defect inspection, Inspection equipment

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Proceedings Article | 30 December 1999 Paper

Reticle defect size calibration using low-voltage SEM and pattern recognition techniques for sub-200-nm defects

Larry Zurbrick, Steve Khanna, Jay Lee, James Greed, Ellen Laird, Rene Blanquies

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373361

KEYWORDS: Scanning electron microscopy, Optical testing, Reticles, LCDs, Pattern recognition, Calibration, Defect inspection, Inspection equipment, Inspection, Photomasks

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