Mr. Rex H. Liu Profile

Rex H. Liu

Engineer at Qoniac Taiwan Ltd

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Author

Publications (9)

Proceedings Article | 22 February 2021 Presentation + Paper

Innovative dual mark design for alignment verification and process monitoring in advanced lithography

Jia Hung Chang, En Chuan Lio, Junjin Lin, Tang Chun Weng, Bill Lin, Patrick Lomtscher, Martin Freitag, Stefan Buhl, Hsiao Lin Hsu, Rex Liu

Proceedings Volume 11613, 116130K (2021) https://doi.org/10.1117/12.2583620

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Proceedings Article | 26 March 2019 Paper

Overlay run-to-run control based on device structure measured overlay in DRAM HVM

Hsiao Lun Chu, Foster Huang, Steven Tottewitz, Boris Habets, Patrick Lomtscher, Hsiao-Lin Hsu, Afu Chiu, Rex Liu

Proceedings Volume 10959, 109592P (2019) https://doi.org/10.1117/12.2515203

KEYWORDS: Overlay metrology, Etching, Device simulation, Feedback control, Lithography, Measurement devices, Semiconducting wafers, Control systems, High volume manufacturing, Inspection

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In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.¹

In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias.

This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.²

This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

Proceedings Article | 26 March 2019 Paper

Alignment sampling by thorough run-to-run simulation

Alex Ren, Ding Kai, Boris Habets, Steffen Guhlemann, Norman Birnstein, Alexander Mühle, Patrick Lomtscher, Rex Liu

Proceedings Volume 10959, 109592O (2019) https://doi.org/10.1117/12.2515001

KEYWORDS: Optical alignment, Overlay metrology, Semiconducting wafers, Optimization (mathematics), Computer simulations, Data modeling, Semiconductors, Metrology, Manufacturing

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Proceedings Article | 26 March 2019 Paper

Intra-field alignment for overlay feed-forward simulation with sampling optimization

Cheng Hao Yang, Chun Chi Yu, Patrick Lomtscher, Martin Freitag, Steven Tottewitz, Boris Habets, Hsiao Lin Hsu, Rex Liu

Proceedings Volume 10959, 109592T (2019) https://doi.org/10.1117/12.2514984

KEYWORDS: Semiconducting wafers, Optical alignment, Data modeling, Overlay metrology, Data corrections, Visualization, Lithography, Reticles, Optimization (mathematics)

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Proceedings Article | 13 March 2018 Paper

Higher order intra-field alignment for intra-wafer lens and reticle heating control

Charlie Chen, En-Chuan Lio, Hsiao Lin Hsu, Jia Hung Chang, Sho Shen Lee, Patrick Lomtscher, Boris Habets, Georg Erley, Norman Birnstein, Steven Tottewitz, Rex Liu

Proceedings Volume 10585, 105851R (2018) https://doi.org/10.1117/12.2297358

KEYWORDS: Optical alignment, Semiconducting wafers, Reticles, Overlay metrology, Data modeling, Neodymium, HVAC controls, Distortion, Calibration, Roads

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Proceedings Article | 13 March 2018 Paper

Advanced combined overlay and CD uniformity measurement mark for double patterning

Hsiao Lin Hsu, En Chuan Lio, Charlie Chen, Jia Hung Chang, Sho Shen Lee, Stefan Buhl, Manuela Gutsch, Patrick Lomtscher, Martin Freitag, Boris Habets, Rex Liu

Proceedings Volume 10585, 105851H (2018) https://doi.org/10.1117/12.2299299

KEYWORDS: Overlay metrology, Etching, Lithography, Semiconducting wafers, Metrology, Critical dimension metrology, Molybdenum, Information operations, Optical lithography, Double patterning technology

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Proceedings Article | 16 March 2009 Paper

Advanced self-aligned double patterning development for sub-30-nm DRAM manufacturing

Weicheng Shiu, Hung Jen Liu, Jan Shiun Wu, Tsu-Li Tseng, Chun Te Liao, Chien Mao Liao, Jerry Liu, Troy Wang

Proceedings Volume 7274, 72740E (2009) https://doi.org/10.1117/12.813986

KEYWORDS: Double patterning technology, Optical alignment, Line edge roughness, Optical lithography, Scanners, Lithography, Extreme ultraviolet, Semiconducting wafers, Etching, Overlay metrology

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Although the Numerical Aperture (NA) has been greatly improved from 0.93 (dry) to 1.35 (wet) by the introduction of modern water immersion 193nm scanner since 2001, the realistic single exposure photolithography printing for mass production is still limited to ~40nm, even with the help of a variety of Resolution Enhancement Techniques (RETs). Theoretically, the 193nm immersion scanner with high index fluid or Extreme UV (EUV) scanner with a significantly shorter wavelength of 13.5nm would be the logical successors to water immersion 193nm scanner. However, considering tremendous technical difficulties to work with high index fluids and relatively immature and very low productivity of EUV at the moment, it's likely that both candidates have little chance to entering production prior to 2012. Additionally, the production schedule can be further pushed out due to formidable initial investment for the costly equipment and consumables associated with EUV given the present worldwide economic recession. Nano-imprint may be attractive for its low cost and versatile nature, however, long-term stability and logistics under production stress yet to be established. The hope to continue the thrust of Moore's Law into the sub-40nm regime before EUV era heavily counts on the success of the so-called Double Patterning Techniques (DPT). A variety of integration schemes have been developed or are still under development to harness the full capacity of DPT. Among them the spacer double patterning approach stands out because of the self-aligned characteristics and a cumulative great deal of experience on the handling of the spacer-related processes in traditional CMOS process integration. The final goal of most research works around Self-Aligned Double Patterning (SADP) focuses on achieving minimal added cost and high quality printing at the same time. However, most of the time the quality and the cost are compromised by applying non-production proven new material/new hardware and/or fancy integration approaches. In our study we purposely apply a more "classical" and relatively conservative integration scheme, with all unit process steps long proven in previous volume production. By carefully optimizing the relative CMP, films deposition, etch and cleaning processes, we are able to demonstrate 30nm line/space patterns by an NA 0.93 dry 193nm scanner with optimal CDU better than 3nm and high frequency line edge roughness (LER) close to 2nm/side. Additionally, by analyzing wafer quality for alignment and alignment residual in various alignment & overlay mark designs, projected residual overlay as little as 4nm can be readily obtained.

Proceedings Article | 27 March 2007 Paper

Double patterning with multilayer hard mask shrinkage for sub-0.25 k1 lithography

Hung Jen Liu, Wei Hsien Hsieh, Chang Ho Yeh, Jan Shiun Wu, Hung Wei Chan, Wen Bin Wu, Feng Yi Chen, Tse Yao Huang, Chiang Lin Shih, Jeng Ping Lin

Proceedings Volume 6520, 65202J (2007) https://doi.org/10.1117/12.711855

KEYWORDS: Double patterning technology, Photomasks, Lithography, Etching, Photoresist processing, Reflectivity, Reactive ion etching, Silicon, Photoresist materials, Neodymium

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Proceedings Article | 21 March 2007 Paper

Proximity effect correction for the chemical shrink process of different type contact holes

Wei Hsien Hsieh, Hung Jen Liu, Wen Bin Wu, Chiang Lin Shin, Jeng Ping Lin

Proceedings Volume 6519, 65193E (2007) https://doi.org/10.1117/12.711944

KEYWORDS: Resolution enhancement technologies, Optical lithography, Photomasks, Lithography, Chemical reactions, Semiconductors, Polymers, Optical design, Optical proximity correction, Coating

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Showing 5 of 9 publications

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