Measuring EPE on logic devices is challenging due to the large variety of features given its random environment and layout. One has to measure an enormous amount of unique features to estimate CD, PPE, LCDU, and LPE of each feature making it impractical for EPE monitoring due to the large metrology load. We developed a simulation-based pattern clustering method that identifies and classifies features with similar EPE behavior to address this challenge. Both geometric design and imaging behavior of the patterns were taken into account to effectively cluster similar features. We report here the verification results of the clustering method which is measured on-wafer for both random layout lines-spaces and vias. With this we make a step towards identification and selection of EPE critical patterns for logic devices, which can be used further for monitoring and control.
The grouping method assisted EPE-aware control method is being explored in a multi-feature dual layer Logic use case. EPE metric is estimated using angle resolved optical Scatterometry based overlay and electron beam-based metrology (large field of view SEM) for the reconstruction of edge-to-edge distance between the Metal and Via pattern. In the setup phase, EPE sensitivities to dose and focus have been derived using data from a FEM wafer. EPE-aware optimization, using scanner dose and overlay control sub-recipes, outperforms traditional optimization in simulations showing reduced EPE max per die. This improvement suggests a potential increase in device yield through the adoption of EPE-aware control strategies. To verify this performance improvement on wafers, an experiment is needed with minimal wafer to wafer and lot to lot variations which can be achieved by reducing time between lots and increasing the number of wafers measured.
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