3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap shows a decrease in the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to small values. In the W2W process, a wafer bonder is used to align and bond two whole wafers. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to ensure the copper pads line up properly before being bonded, driving an increased need for overlay metrology precision and die-bonder control. The bonded wafers are subsequently cut up into stacked chips using a dicing process and then undergo testing and further packaging. Advanced processing control (APC) for W2W hybrid bonding is an important factor in fulfilling the target on-product overlay (OPO) via litho inputs, in-plane distortion (IPD), overlay (OVL) and bonder correction knobs. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget.
Sub-2nm On Product Overlay (OPO), scribe line width reduction, and high-order scanner correctibles are driving innovative overlay (OVL) targets. One promising new imaging-based overlay (IBO) OVL target to address such challenging trends in multiple semiconductor segments is a small pitch AIM (sAIM). sAIM is in essence an IBO target with grating (previous layer) beside grating (current layer) which could be placed in a few layouts: square, rectangular, and Mosaic. In this work, we will present the sAIM operational concept and performance including Total Measurement Uncertainty (TMU), residuals, and accuracy (ADI on-target offset vs. ACI on-device or target), which is often referred to as Non-Zero Offset (NZO).
As 3D NAND devices increase memory density by adding layers, scaling and increasing bits-per-cell, new overlay (OVL) metrology challenges arise. On product overlay (OPO) may decrease for critical thick layers such as thick deck-to-deck alignment, whereas high aspect ratio (Z-axis) structures introduce stress, tilt and deformation that require accurate and robust OVL measurements. Advanced imaging metrology (AIM®) targets, that consist of two side-byside periodic gratings in the previous and current layers, are typically used to measure OVL with Imaging Based Overlay (IBO) metrology systems. In this paper, we present a new approach that utilizes the Talbot effect in AIM to produce multiple contrast planes along the Z-axis, which enables a common focus position for both layers at a similar focus plane, resulting in improved measurement robustness. We will present Talbot effect theory, target design steps by metrology target design (MTD) simulator, actual measurement results on an advanced 3D NAND device and conclusions for such targets.
The current state of the art ADI overlay metrology relies on multi-wavelength uDBO techniques. Combining the wavelengths results in better robustness against process effects like process induced grating asymmetries. Overlay information is extracted in the image plane by determining the intensity asymmetry in the 1st order diffraction signals of two grating pairs with an intentional shift (bias). In this paper we discuss a next evolution in DBO targets where a target is created with multiple biases. These so called cDBO (continuous bias DBO) targets have a slightly different pitch between top and bottom grating, which has the effect of having a different bias values along the grating length and are complimentary to the uDBO technology. Where for the uDBO target, the diffraction results in a uniform Intensity pattern that carries the Overlay signal, for cDBO, an oscillating intensity pattern occurs, and the Overlay information is now captured in the phase of that pattern. Phase-based Overlay has an improved, intrinsic robustness over intensity-based overlay and can reduce the need for multi-wavelength techniques in several cases. Results on memory technology wafers confirm that the swing-curve (through-wavelength) behavior is indeed more stable for phase-based DBO target and that for accurate Overlay, this target can be qualified with a single wavelength recipe (compared to the uDBO dual wavelength recipe). In this paper, both initial results on a Micron feasibility wafer will be shown as well as demonstrated capability in a production environment.
Low k1 lithography poses a number of challenges to the process development engineer. Although polarization and
immersion lithography will allow us to create processes at lower k1 than previous paradigms allowed, the lithographer
will quickly be looking for Resolution Enhancement Techniques (RET) to push to the ultra-low k1 regime, or to extend
older generation tools and avoid the aforementioned expensive options. Reticle transmission is a RET that can enable a
low k1 process by increasing image contrast. With work performed in conjunction with our MP Mask facility, we have
been able to obtain custom-transmission EAPSM reticles. Reticle transmission optimization can be carried out through
simulation. Optimum transmission varies depending on optical parameters and feature size. Moreover, when working
with 2D patterns, reticle transmission can be optimized for weaker features, without significantly sacrificing image
contrast on primary features.
Process improvement by optimizing reticle transmission will be explored for a variety of device types using both 248nm
and 193nm lithography. Simulation, custom-transmission reticle fabrication, and empirical wafer results will be
presented.
Successful developer-soluble topcoats have to fulfill numerous requirements; specifically they have to serve as a barrier layer and be compatible with the resist. Some of the requirements and compatibility issues have been understood; others are still under-investigation by the joint efforts of lithographers and resist chemists. This paper addresses these requirements from the perspective of overall lithographic performance for developer-soluble topcoats used in 193nm water immersion lithography. We demonstrate that with the optimized combination of resist and developer-soluble topcoat 90nm 1:1 dense lines can be printed using a prototype tool, ASML AT 1150i, and a binary image mask (BIM) with a maximum depth-of-focus (DOF) of ~1.2μm. An approximate 2X DOF improvement over dry lithography that was theoretically expected has been truly demonstrated. Topcoat related defectivity as well as defect reduction efforts are also discussed.
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