One of the key methods targeted for continuing the resolution scaling in new device technology nodes is the trend towards using curvilinear mask patterns. With recent advances in multi-beam mask patterning and large-scale adoption of ILT mask data correction, curvilinear (and all-angle) mask patterns are considered today as a mainstream technology option. Curvilinear mask patterns provide improved wafer resolution and OPC/ILT mask correction control with reduced mask manufacturing issues related to tight corners and line-ends. However, OPC, ILT, LRC and other full-chip simulation-based mask synthesis methods also require more accurate electromagnetic (i.e., M3D) simulation for new technology nodes. Prior full-chip electromagnetic simulation methods have often assumed that mask patterns are restricted to Manhattan geometries or utilize limited angles. Therefore, there is a general industry need for improved electromagnetic full-chip simulation methods for curvilinear mask patterns. This paper will present a new electromagnetic full-chip simulation method for curvilinear mask patterns that will improve the accuracy of mask synthesis methods at upcoming technology nodes. This method can provide both accuracy and speed benefits on mask synthesis with curvilinear mask patterns for both DUV and EUV lithography. The method utilizes an enhanced physics-based treatment of electromagnetic mask scattering both tuned and verified by rigorous electromagnetic Maxwell’s equation solvers.
EUV lithography has been ramped to successful volume manufacturing through a combination of improvements in process technology, layout design and device interactions, and also optimization of the overall product integration to reduce undesirable interactions. Because EUV has additional sources of systematic and stochastic variation that did not exist in DUV lithography, it is now even more important to have accurate predictive capability to test and understand the design and lithography process interactions. EUV-specific physical behavior such as shadowing, flare, mask topography (i.e., Mask3D) effects, mask stack reflectivity, mask absorber behavior and other effects are key differences in how EUV forms an image on the mask and subsequently on the wafer. The reflective mask substrate and EUV-specific mask absorber stack are therefore highly important technologies to optimize as the industry pushes both low NA (0.33NA) and high NA (0.55NA) technologies to cover the patterning requirements of upcoming 3nm and below technology nodes. Recently there have been substantial industry interest in optimizing EUV mask stacks to further enhance imaging behavior and achieve better pattern resolution, increase process window, lower stochastic defectivity and optimize flare. Several different options have been proposed for these new EUV mask stacks for lower K1 EUV patterning. All of these new options require excellent simulation accuracy in OPC, SrAF placement, OPC verification and ILT mask synthesis steps in order to realize the benefits of the new mask stacks. In this paper we will focus on analyzing and improving the accurate prediction of a range of new EUV mask stack options for full-chip OPC/ILT compatible compact models. We will show for advanced mask designs the accuracy requirements and capability of leading-edge compact models. The accuracy requirements and capability will be referenced to fully rigorous electromagnetic solver (e.g., Mask3D) results to ensure industry needs are met. We will also explore the mask stack options to highlight the imaging benefits for different material thickness, refractive index (n) and extinction coefficient (k) on important mask pattern feature and layer types.
The technological demands on the semiconductor industry continuously require shrinking feature critical dimensions (CDs) and improved feature CD control. To meet feature CD demands requires advances in DUV and EUV lithography as well as improvements in photoresists, including negative tone-development (NTD) and positive tonedevelopment (PTD), materials properties and processing. As an example, the semiconductor industry has benefited from significant improvements in 193nm lithographic resolution and process window with NTD photoresist (resist) patterning processes of trench and hole/via features. Consequently, optical proximity correction (OPC) compact modeling of NTD resists has needed to advance to accurately model the different chemical and physical material properties, including the deformation, of thin films. From a fundamental point of view, while the basic deformation and shrinkage behavior observed in NTD resists is captured by rigorous and compact simulators, there remains known complex phenomena, such as polymer entanglements, strain softening, and strain hardening, in the materials science community, that are not present in the current models applied in OPC. In this paper, we describe these phenomena and, where appropriate, their impact on compact and rigorous resist modeling. Finally, we discuss how these newly addressed deformation effects may improve overall OPC accuracy and therefore enable further feature CD reduction and control.
PTD photoresists are still the main type of photoresists used for tight pitch layers in advanced patterning. Recent experimental results show evidence that the same mechanical deformation behaviors seen in NTD photoresist process also exist in PTD photoresist processes. These PTD photoresist deformation behaviors cause CD differences which significantly impact CD control budgets in modern technology nodes. Therefore, there is a strong need to accurately model PTD photoresist deformation effects in compact OPC models. In this paper we discuss the polymer physics relevant to physical deformation in PTD photoresists in comparison to NTD photoresists
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