Model based optical proximity correction (MB-OPC) has been widely used in advanced lithography process today.
However controlling the edge placement error (EPE) and critical dimension (CD) has become harder as the k1 process
factor decreases and design complexity increases. Especially, for high-NA lithography using strong off-axis
illumination (OAI), ringing effects on 2D layout makes CD control difficult. In addition, mask rule check (MRC) limits
also prevent good OPC convergence where two segment edges are corrected towards each other to form a correction-conflicting
scenario because traditional OPC only consider the impact of the current edge when calculating the edge
movement. A more sophisticated OPC algorithm that considers the interaction between segments is necessary to find a
solution that is both MRC and convergence compliant.
This paper first analyzes the phenomenon of MRC-constrained OPC. Then two multiple segment correction techniques
for tolerance-based OPC and MRC-constrained OPC are discussed. These correction techniques can be applied to
selected areas with different lithographic specifications. The feasibility of these techniques is demonstrated by
quantifying the EPE convergence through iterations and by comparing the simulated contour results.
In this paper, we present some important improvements on our process window aware OPC (PWA-OPC). First, a CDbased
process window checking is developed to find all pinching and bridging errors; Secondly, a rank ordering method
is constructed to do process window correction; Finally, PWA-OPC can be applied to selected areas with different
specifications for different feature types. In addition, the improved PWA-OPC recipe is constructed as sequence of
independent modules, so it is easy for users to modify its algorithm and build original IPs.
Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask
proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include
the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict
the entire lithography process correctly even using advanced optical and resist models. In order to compensate
for the mask proximity effect within OPC a special model is required along with changes to the OPC flow.
This article presents a method for producing such a model and OPC flow and shows the difference in results
when they are used.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model
capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and
more difficult to maintain because of very small process windows in specific situations. These specific situations
include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations.
In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process
windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more
traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well
characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering
In this paper the method of Process Window aware OPC is applied on special designed test structures and on a
larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past
OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be
successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can
still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to
introduce complicated design constraints.
Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The
repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay
issues while accuracy of first pattern is critical for the space technology. Both technologies
require improved model accuracy and process margin. Because of this, even traditionally noncritical
regions of a layout may contain process margin-limiting defects for double patterning
technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve
quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast
OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a
thorough check of the OPC results, including process window analysis. This determines which
points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas
limiting process margin. These advanced OPC techniques may include broader lithographic
analysis, field-based correction and process window consideration. Since advanced OPC
methods are only applied to part of the design, TAT is fast. TAT can be further improved by
treating critical regions differently. Critical regions will not be processed in the initial OPC or
intermediate verification steps, but will be corrected by the advanced OPC methods. This
methodology is called Incremental OPC as it applies the most appropriate OPC techniques to
each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution
assist feature printing can be eliminated prior to mask tape-out with minimal impact
to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which
must be applied across an entire pattern.
The upcoming 45nm and 32nm device generations will continue the familiar industry lithography trends of
decreased production K1 factor, reduced focus error tolerances and increased pattern density. As previous
experience has shown, small changes in the values of lithographic K1, focus tolerance and pattern density
for the process-design space can lead to large required changes in OPC and RET solutions. Therefore,
significant improvements in utility and speed are needed for these new device generations. In this paper we
highlight significant new functionality and performance capabilities using existing Field-based OPC and
RET methods. The use of dense grid calculations in Field-based methods is shown to provide a software
platform for robust and fast implementation of new model-based RET techniques such as model-based
assist feature placement and tuning. We present the performance and capability increases for model-based
RET methods. Additionally, we have studied and present the performance of production 45nm generation
field-based OPC and RET software across several different multiple-purpose hardware platforms.
Significant improvements in runtime (for approximately the same hardware cost) are observed with new
general purpose hardware platforms and with software optimization for this hardware.
The upcoming 45nm device node is a point at which newer field-based (i.e., dense pixel-based) OPC simulation methods may begin to show advantages over sparse-sampling ("flash") simulation methods. Field-based simulation provides computational efficiencies in applications where a large number of model evaluation locations are needed, and where the simulated layout geometry is complex. Field-based simulation leverages computation in the frequency domain, whereas sparse-sampling methods operate in the space domain. Mathematically, both methods are equivalent but their respective numerical methods give rise to some implementation differences for OPC applications. These differences include different optimization strategies for hierarchical processing, and fine-grained feature symmetry control for critical matched-transistor circuits (such as SRAM, where noise margin is a fundamental device control issue). An optimum, field-based OPC solution will address these differences without compromising the performance benefits of field-based methods. In this paper we describe and compare the manufacturing implementation of flash-based and field-based OPC at the 45nm and 32nm device nodes
Optical Proximity Correction improves wafer image fidelity by combining small correction shapes with the original pattern data. Although these small shapes improve the exposure of the wafer image, the increase in total figure count results in longer fracture processing and E-beam writing time to create the mask. In this paper we describe alternative OPC treatment for jogs on non-Manhattan features, which reduce the additional figures produced, and make the data friendlier to the fracture and mask fabrication phases. Illustrations of example pattern data and improvement results in terms of figure counts are described.
An integrated methodology for developing recipes for optical proximity correction (OPC) is demonstrated. A complete implementation of software programs for generating the OPC corrections, determining mask and layout errors and automatically displaying contours of the worst violations has been accomplished. Integration of these elements facilitates recipe development by quantifying the effect of recipe changes on the overall critical dimension (CD) control. In this paper, a 65nm alternating aperture phase shift test mask is used for illustration of the method. The concept of a recipe comparison matrix is introduced to quantify the effect of recipe changes on across-chip metrics.
Optical Proximity Correction (OPC) improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. Although the presence of these small shapes improves the final wafer image quality, it causes an increase in total figure count, longer fracture processing time, and the introduction of sliver figures. These undesirable artifacts can have a negative impact on the mask write time and mask image quality. In this paper we outline alternative OPC treatments which reduce the additional figures produced, and make the layout configurations friendlier to the subsequent mask fabrication phase. These include the alignment of neighboring small shapes during the OPC operation, and the preservation of jog alignment during the biasing phase. Illustrations of example pattern data, and improvement results in terms of figure counts are described.
With the exponential increase in output database size due to the aggressive optical proximity correction (OPC) and resolution enhancement technique (RET) required for deep sub-wavelength process nodes, the CPU time required for mask tape-out continues to increase significantly. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround of a mature, plain-vanilla CMOS process of around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes.
Unlike silicon processing, masks tape-out time can be decreased by simply purchasing extra computing resources and software licenses. Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue.
Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl’s law. Very few are efficient enough to allow the effective use of 1000’s of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.
As the industry moves to 90nm and below, the size of our process windows are rapidly decreasing. The process window is often not considered during optical proximity correction (OPC) which must match the printed wafer to the original design target for a single process point. This process point is usually at 'best exposure' and 'best defocus'. The results can be verified under different defocus conditions but it is generally assumed that the printed pattern will yield well for a range of defocus and exposure conditions. At 90nm or smaller this assumption is breaking down as the final yield of products is greatly reduced due to low pattern quality under even relatively small process variations.
Instead of optimizing the OPC results using a single model a multi-model approach is proposed where the pattern is optimized using two or more process points. The final printed image is optimized to both minimize the overall CD variations across a process as well as centering this variation with respect to the original target edges in CD critical areas. To maximize the benefits of this technique we also provide more freedom to OPC by making use of design intent to vary the print requirement in different areas of the design. In this paper we describe the process centering methodology and its use of design intent. To evaluate the benefits of this technique a metric is also proposed and used to quantify experimental results. Results are compared with those of a traditional OPC flow.
Mask fabrication rules can interfere with the ability of OPC and RET shape generation to achieve the best lithographic quality on silicon. With low k1 lithography, ideal correction shapes dictated by lithography-based simulation frequently violate mask geometry constraints. Because the scaled spatial bandwidth of the wafer lithography process is lower than that of the mask process there are some degrees of freedom in OPC shape generation to optimize for lithographic accuracy and mask compliance together. In this paper we discuss strategies to embed mask rule compliance in correct-by-construction model-based OPC.
For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.
The computational power needed to generate mask layouts for OPC and resolution enhancement techniques increases exponentially with process node. Rapidly growing design complexity is compounded with the more aggressive methods now required for smaller feature sizes. Layers once considered non-critical now routinely receive correction. While some improvement in code efficiency can be expected, algorithms are maturing to the point where improvements will likely not keep pace with the computational need. To maintain required processing cycle times massively parallel processing methods must be employed.
In this paper we discuss loosely-coupled distributed computing architectures applied to OPC/RET layout synthesis. The degree to which an application is scalable depends on how well the problem can be divided into independent sets of data. Furthermore, data must also be partitioned into reasonably sized blocks so that memory requirements per processor can be bounded. Communication overhead, I/O overhead and serial processeses all degrade scalability, and may increase overall storage requirements. In this paper we analyze behavior of distributed processing architectures with large numbers of processors, and we present performance data on an existing massively parallel system.
In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.
In its purest form optical proximity correction (OPC) creates a mask layout to faithfully reproduce the design intent, or target, on silicon. Practical, production-worthy OPC deviates from this ideal in several respects. First, each set of anticipated process conditions -- defocus, dose -- would require a unique ideal correction. An optimized OPC shape must be derived to minimize harm over the expected ranges of process conditions. Second, the original design layout does not always convey accurate or complete information about the design intent. For example, square corners cannot be printed; how much corner rounding is acceptable? Some legacy design practices, such as line-end extension rules, anticipate (in part) proximity-effects where the intended line end is shorter than drawn. Without additional information, the OPC tool is constrained to aim for the one silicon layout matching the drawn layout as closely as possible. On the other hand, if the OPC tool is given limited liberty to deviate from drawn shapes and positions where they have little or no impact on circuit behavior the correction can be better optimized for several, sometimes competing, constraints - such as: minimizing output figure complexity, minimizing CD error through process variation, maximizing image contrast, and minimizing mask error enhancement factor. In this paper we will demonstrate OPC strategies for optimizing corrections to minimize the harmful effects of random process variations while simultaneously minimizing mask layout complexity. We introduce the concept of a 'conformal target' layout which enhances the drawn pattern with design-intent tolerance information. This information specifies bounds on minimum line and space dimensions, line position, and edge position. Such feature-specific tolerance information provides additional degrees of freedom for OPC synthesis to optimize trade-offs among process window behavior, contrast, MEEF reduction, output figure complexity, and other fab-specific objectives. Furthermore, the tolerance-based conformal target provides an ideal reference pattern for verifying OPC and other resolution enhancement treatments (RET) on the mask layout.