In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors constitute inputs for trained classifiers which in turn enable different high-level vision tasks. While local descriptors certainly alleviate the computation load of subsequent processing stages by preventing them from handling raw images, they still have to deal with individual pixels. Feature vector extraction can thus become a major limitation for conventional embedded vision hardware. In this paper, we present a power-efficient sensing processing array conceived to provide the computation of integral images at different scales. These images are intermediate representations that speed up feature extraction. In particular, the mixed-signal array operation is tailored for extraction of Haar-like features. These features feed the cascade of classifiers at the core of the Viola-Jones framework. The processing lattice has been designed for the standard UMC 0.18μm 1P6M CMOS process. In addition to integral image computation, the array can be reprogrammed to deliver other early vision tasks: concurrent rectangular area sum, block-wise HDR imaging, Gaussian pyramids and image pre-warping for subsequent reduced kernel filtering.
KEYWORDS: Signal to noise ratio, Logic, Interference (communication), Modulators, Quantization, Electronic filtering, Tolerancing, Standards development, Global system for mobile communications, Lawrencium
This paper presents innovative architectures of hybrid Continuous-Time/Discrete-Time (CT/DT) cascade ΣΔ Modulators
(ΣΔMs) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth
as compared to conventional ΣΔMs, the proposed topologies take advantage of the CT nature of the front-end ΣΔM stage,
by embedding anti-aliasing filtering as well as their suitability to operate up to the GHz range. Moreover, the presented
modulators include multi-bit quantization and Unity Signal Transfer Function (USTF) in both stages to reduce the integrator
output swings, and programmable resonation to optimally distribute the zeroes of the overall Noise Transfer Function
(NTF), such that the in-band quantization noise is minimized for each operation mode. Both local and inter-stage
(global) based resonation architectures are synthesized and compared in terms of their circuit complexity, resolution-bandwidth
programmability and robustness with respect to circuit non-ideal effects. The combination of all mentioned characteristics
results in novel hybrid ΣΔMs, very suited for the implementation of adaptive/reconfigurable Analog-to-Digital
Converters (ADCs) intended for the 4th Generation (4G) of wireless telecom systems.
This paper reports a 130-nm CMOS programmable cascade &Sgr;&Dgr; modulator for multi-standard wireless terminals, capable
of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit-
level in order to adapt its performance to the different standards specifications with optimized power consumption.
The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical
optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards,
featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.
KEYWORDS: Transceivers, Silicon, Amplifiers, Modulators, Telecommunications, Analog electronics, Standards development, Global system for mobile communications, Phase only filters, Evolutionary algorithms
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single
terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital-Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements:
(1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and
performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels,
with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated
annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design
information. The systematic design methodology is illustrated via the design of a multi-standard &Sgr;&Dgr; modulator meeting the
specifications of three wireless communication standards.
This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver frontends.
The toolbox includes a library with the main RF circuit models that are needed to implement wireless transceivers,
namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including
other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral
models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise
characterized by the Noise Figure (NF) and the Signal-to-Noise Ratio (SNR) and nonlinearity expressed by the input-referred
2nd- and 3rd-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some
block specific errors have been also included, like oscillator phase noise and mixer offset. These models have been incorporated
into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of
library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed
toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As
an application of the capabilities of the presented toolbox, a multi-standard Direct-Conversion Receiver (DCR) intended
for 4G telecom systems is modeled and simulated considering the building-block requirements for the different standards.
This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C).
The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔΜ topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy.
The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.
Smart sensors play a critical role in modern automotive electronic systems, covering a wide range of data capturing functions and operating under adverse environmental conditions - temperature range of [-40ºC,175ºC]. In such sensors, the signal provided by transducers is composed of an offset voltage, which depends on the manufacturing process, and a low-frequency signal carrying the information. In practice, the offset voltage is subject to temperature variations, thus causing a shifting of the signal range to be measured. Therefore, the measuring circuit driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC), must accommodate the complete range of possible offsets and real signals. In this scenario, the use of ADCs based on Sigma-Delta Modulators (SDMs) is convenient for several reasons. On the one hand, the noise-shaping performed by SDMs allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of SDMs with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation. This feature allows to accommodate the complete range of possible offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes the design and implementation of a third-order cascade (2-1) SDM with programmable gain in a 0.35mm CMOS technology - the type of technology commonly employed for automotive applications (deep submicron is mostly employed for telecom). It is capable of handling signals up to 20-kHz bandwidth with 17-bit resolution. The programmable gain is implemented by a capacitor array whose unitary capacitors are connected or disconnected depending on the value of the selected gain. In order to relax the amplifier dynamics requirements as the modulator gain varies, switchable capacitor arrays have been used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. As a result, a dynamic range equal to 105 dB is obtained for all cases of the modulator gain, which corresponds to 17 bit resolution.