This will count as one of your downloads.
You will have access to both the presentation and article (if available).
Metal containing resists (MCR) are one of the candidates for extreme ultraviolet resists aiming to achieve the resolution, linewidth roughness, and sensitivity requirements of advanced design nodes. MCRs intrinsically have high etch resistance owing to their metal content. Therefore, low resist thickness (∼18 nm) is sufficient to transfer resist patterns into an underlying hard mask. Also, the thin resist reduces susceptibility to pattern collapse during development because of low aspect ratio. However, thus far, little attention has been paid to optical metrology and inspectability (overlay, defect inspection, scatterometry, etc.) of these resists, which is another critical requirement to move MCR toward high-volume manufacturing. We investigate the overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR), it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.
In this paper, we investigate overlay metrology and overlay correction with MCR. Even though the optical contrast for MCR is slightly lower than for chemically amplified resist (CAR) it seemed sufficient for high-quality overlay metrology. However, the measurement precision for MCR is deteriorated compared to that for CAR, resulting in significantly higher residuals. The root cause of the deteriorated measurement precision was found in grains in the optical image after MCR development. Interestingly, the after etch performance of CAR and MCR is identical. We demonstrate that with sufficient sampling, appropriate correctables can be extracted from the MCR overlay results. Finally, we discuss how the increased image noise can be compensated by the applied sampling scheme.
Via patterning in the 7-nm node using immersion lithography and graphoepitaxy directed self-assembly
In this paper, we propose a new generation of software platform and development infrastructure which can integrate specific metrology business modules. For example, we will show the integration of a chemistry module dedicated to electronics materials like Direct Self Assembly features. We will show a new generation of image analysis algorithms which are able to manage at the same time defect rates, images classifications, CD and roughness measurements with high throughput performances in order to be compatible with HVM. In a second part, we will assess the reliability, the customization of algorithm and the software platform capabilities to follow new specific semiconductor metrology software requirements: flexibility, robustness, high throughput and scalability. Finally, we will demonstrate how such environment has allowed a drastic reduction of data analysis cycle time.
Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced.
For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.