We present an experimental study of pattern variability and defectivity, based on a large data set with more than 112 million SEM measurements from an HMI high-throughput e-beam tool. The test case is a 10nm node SRAM via array patterned with a DUV immersion LELE process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to a seemingly qualitative differences in defectivity. The large available data volume enables further analysis to reliably distinguish global and local CDU variations, including a breakdown into local systematics and stochastics. A closer inspection of the tail end of the distributions and estimation of defect probabilities concludes that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. We expect that the analysis methodology can be applied for defect probability modeling as well as general process qualification in the future.
In the advent of multiple patterning techniques in semiconductor industry, metrology has progressively become a burden. With multiple patterning techniques such as Litho-Etch-Litho-Etch and Sidewall Assisted Double Patterning, the number of processing step have increased significantly and therefore, so as the amount of metrology steps needed for both control and yield monitoring. The amount of metrology needed is increasing in each and every node as more layers needed multiple patterning steps, and more patterning steps per layer. In addition to this, there is that need for guided defect inspection, which in itself requires substantially denser focus, overlay, and CD metrology as before. Metrology efficiency will therefore be cruicial to the next semiconductor nodes. ASML's emulated wafer concept offers a highly efficient method for hybrid metrology for focus, CD, and overlay. In this concept metrology is combined with scanner's sensor data in order to predict the on-product performance. The principle underlying the method is to isolate and estimate individual root-causes which are then combined to compute the on-product performance. The goal is to use all the information available to avoid ever increasing amounts of metrology.
As leading edge lithography moves to advanced nodes, CDU requirements have relatively increased with technologies 14nm/20nm and beyond. In this paper, we want to introduce the methodology to offer an itemized CDU budget such as Intra-field, Inter-field, wafer to wafer as well as scanner contributors vs. non-scanner contributors (including detailed analysis of reticle contributors like CD, absorber thickness and SWA variation) through Top-Down CDU and Bottom-Up CDU budget breakdown and deliver sources of CD variation with measureable value so that we can estimate CDU gain from them. The test vehicle being used in this experiment is designed based on 14nm D/R basis. Measurement structures are densely located in the slit/scan direction on the reticle for the data collection plan. Hence, we can expand on this methodology to build up the tool reference fingerprint when we release new tool fleet. The final goal will be to establish a methodology for CDU budget breakdown that can be used to draw a conclusion on the root causes of the observed CDU, propose its improvement strategy and estimate the gain.
Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX
KEYWORDS: Lithography, Metrology, Optical lithography, Defect detection, Detection and tracking algorithms, Data modeling, Deep ultraviolet, Sensors, Etching, Scanners, Inspection, Scanning electron microscopy, Process control, High volume manufacturing, Semiconducting wafers
As process window margins for cutting edge DUV lithography continue to shrink, the impact of systematic patterning defects on final yield increases. Finding process window limiting hot spot patterns and monitoring them in high volume manufacturing (HVM) is increasingly challenging with conventional methods, as the size of critical defects can be below the resolution of traditional HVM inspection tools. We utilize a previously presented computational method of finding hot spot patterns by full chip simulation and use this to guide high resolution review tools by predicting the state of the hot spots on all fields of production wafers. In experiments with a 10nm node Metal LELELE vehicle we show a 60% capture rate of after-etch defects down to 3nm in size, at specific hot spot locations. By using the lithographic focus and dose correction knobs we can reduce the number of patterning defects for this test case by ~60%.
In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.