As IC density shrinks based on Moore’s law, optical lithography continually is scaled to print ever-smaller features by using resolution enhancement techniques such as phase shift mask, optical proximity correction (OPC), off-axis illumination and sub-resolution assistant features. OPC has been playing a key role to maximize the overlapping process window through pitch in the sub-wavelength optical lithography. As an important cost control measure, one general OPC model is applied to the full exposure field across multiple scanners. To implement this technique, optical proximity matching of line width across the field and across multiple tools turns out to be very crucial particularly at gate pattern. In addition, it is very important to obtain reliable critical dimension (CD) data sets with low noise level and high accuracy from the metrology tool. Otherwise, extracting the real scanner fingerprint in term of CD can not be achieved with precision in the order of 1nm~2nm. Scatterometry CD measurements have demonstrated excellent results to overcome this problem. The methodology of Scatterometry is emerging as one of the best metrology tool candidates in terms of gate line width control for technology nodes beyond 130nm.
This paper investigates the sources of error that consume the CD budget of optical proximity matching for line through pitch (LTP). The study focuses on the 130nm technology node and uses experimental data and Prolith resist vector model based simulations. Scatterometer CD measurements of LTP are used for the first time and effectively correlated to lens aberrations and effective partial coherence (EPC) measurements which were extracted by Litel In-situ Interferometer (ISI) and Source Metrology Instrument (SMI). Implications of optical proximity matching are also discussed for future technology nodes. From the results, the paper also demonstrates the efficacy of scatterometer line through pitch measurements for OPC characterization.
Conventional and annular illumination modes for a 248 nm DUV scanner will be discussed in this paper for their advantage and drawbacks in critical dimension (CD) control. This includes proximity of line width through pitch size, marginality of resist profile measured as sidewall angle, depth of focus (DOF) in line width variation across field/wafer, and isolated space resolution, supported by SEM and scatterometer metrology. Both illumination modes have been applied in the current technology node with sub-wavelength CD, variable pitch sizes, optical proximity correction (OPC) for resolution enhancement and process control optimization. Each illumination defines process margin in exposure, focus and CD uniformity, to gain capability with improved CD control.
Gate critical dimension (CD) uniformity across field is a key parameter in total gate CD control; it is especially important for highly integrated microprocessor chip with large die size and high speed. Intensive study has been conducted to reveal the impact of scanner leveling tilt, defocus and illumination distribution on CD uniformity across field. Correspondingly CD in die range, vertical-horizontal CD bias, resist side wall angle and profile have all been characterized and monitored for each individual scanner. The monitoring methodology we have established enables us to maintain these CD parameters within fairly tight control range, and also provided efficient and accurate data on tool capability and marginality for running production.
The impact of reticle imperfections on resist critical dimension (CD) variation has greatly increased as design rules shrink to smaller than exposure wavelength. Resolution enhancement techniques, such as optical proximity correction (OPC) and phase-shift mask (PSM), add a great deal of complexity to the mask manufacturing process. Stringent requirements in wafer processing make reticles a crucial factor in CD control. However, making a perfect reticle is a significant challenge for mask manufacturers. In this paper, the strong correlation between reticle and resist CD variation is reported. Multiple sources of hidden CD errors due to imperfect reticles are discussed. Examples include butting errors, grid snapping, OPC model incompatible among reticles with same design rule but with different mask processes, phase-angle and transmission variations in PSM, undetectable reticle defects from reticle inspection, and small reticle defects that are often classified as 'false' defects. Root causes are analyzed and procedures to minimize hidden CD errors are proposed.