Proceedings Article | 30 December 2008
Sang-Hoon Baek, Ha-Young Kim, Young-Keun Lee, Duck-Yang Jin, Se-Chang Park, Jun-Dong Cho
KEYWORDS: Metals, Computer aided design, Standards development, Design for manufacturing, Logic, Multiplexers, Transistors, Design for manufacturability, Silicon, Manufacturing
As the market size of mobile products is enlarged, low power and high density design in integrated chips are
demanding. To meet these market demands, "ultra high density" (UHD) standard cell library becomes essential to further
reduce the chip size. Furthermore, to enhance the density of standard cell library especially at 90nm and below, the
conventional methods of reducing cell height is not sufficient to meet the density constraints. Motivated by the fact, in
this paper, we devise a flexible design technique of UHD library with the multi-height cell structure. Each cell of
conventional standard cell libraries with one-layer metal routing has the same cell height. However, multi-height cell
library with two-layer metal routing has two types of cell structure: 1) Simple cells (e.g. inverter, nand, nor, etc.) are
structured with single height; 2) Complex cells (e.g. flip-flop, latch, mux, etc.) are structured with double height. In this
double height cell structure, Metal2 layer is used for power line. Therefore, Metal1 and G-ploy are routed vertically,
gaining more Metal1 routing space, and thus we can attain more effective design for manufacturability (DFM). Also, by
doing so, design time is reduced while achieving better layout efficiency. We tested logic circuits with 700,000 gates
using 90nm technology to compare our new UHD library with existing high density library. Our experimental results
show that each of 26 cells (frequently used) is shrunk by 14.29 ~ 26.98%. Furthermore, chip size is shrunk by 13.90 ~
15.65% compared with high density library.
