As semiconductor technologies move toward 90nm generation and below, contact hole is one of the most challenging
features to print in the semiconductor manufacturing process. There are two principal difficulties in order to define small
contact hole pattern on wafer. One is insufficient process margin besides poor resolution compared with line & space
pattern. The other is that contact hole should be made through pitches and sometimes random contact hole pattern should
be fabricated. Therefore advanced ArF lithography scanner should be used for small contact hole printing with RETs
(Resolution Enhancement Techniques) such as immersion lithography, OPC(Optical Proximity Correction), PSM(Phase
Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), mask
biasing and thermal flow. Like this, ArF lithography propose the method of enhancing resolution, however, we must
spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF.
In this paper, we suggest the method of contact holes patterning by using KrF lithography tool in 90nm sFlash(stand
alone Flash)devices. For patterning of contact hole, we apply RETs which combine OAI and Model based OPC.
Additionally, in this paper we present the result of hole pattern images which operate ArF lithography equipment. Also,
this study describes comparison of two wafer images that ArF lithography process which is used mask biasing and Rule
based OPC, KrF lithography process which is applied hybrid OPC.
In low-k1 imaging lithography process it is difficult to make the accurate OPC model not only because of factors caused
by unstable process such as large CD (Critical Dimension) variation, large MEEF (Mask Error Enhancement Factor) and very poor process window but also because of potential error factors induced during OPC model fitting. In order to minimize those issues it is important to reduce the errors during OPC modeling. In this study, we have investigated the most influencing error factors in OPC modeling. At first, through comparing influence of optical parameters and illumination systems on OPC runtime and model accuracy, we observe main error factor. Secondly, in the case of resist modeling, OPC runtime and model accuracy were also analyzed by various model forms.
The methodology of lithography friendly design (LFD) has been widely adopted since it dramatically reduces cycle of
design revision as well as number of learning cycles to reach acceptable yield. LFD is, for example, the reduction
number of small jogs and notches in original, pre-OPC layouts. We can call them as OPC-unfriendly patterns since they
create unnecessarily complicated OPC patterns. They usually meet design rule so that DRC does not detect or screen
them out. Also, they make many errors after OPC because OPC model recognizes just as one of small features that it
should care. This generates many false alarms at OPC verification and mask rule check.
General approach to implement LFD is to update rule table or design rule by taking actual yield and failure analysis
data into consideration of database handling flow. Another method is the utilization of simulation to predict lithography
unfriendly designs. It takes time to setup excellent rule for accurate prediction even if they are very good approach as
fundamental solution for LFD. It will be better to have a simple solution with fast setup and improvement on major
lithography unfriendly designs such as small jogs and notches.
In this paper, we proposed new type of LFD flow which is the application of modified DRC step on LFD flow. This
modified DRC identifies OPC-unfriendly patterns, and changes to "OPC-friendly" as well as fixing design rule
violations. It is a pre-OPC layout treatment to remove small jogs and notches. After finding small jogs or notches, DRC
software removes jogs and notches. In this case, unnecessary OPC fragments could be avoided. Using this jog-fill
technique, we can dramatically reduce the incidence of necking or bridging, improve contact coverage, and, as a result, it
enhances the final yield and reliability of circuit.
As the resolution requirement downing 90 nm beyond, hole pattern is one of the most challenging features to print in
the semiconductor manufacturing process. Especially, when hole patterns have dense array of holes as they are consisted
of several columns with single row, there can be serious distorted form from desired patterns such as oval hole shape and
bridge between holes. It is due to nature of diffraction which generates interaction of diffracted light from near holes.
Overlap margin reduction by hole shape change as oval shape is very harmful in sub-90nm photolithography process
which has very narrow overlay margin. To increase overlap margin, it is necessary to solve these phenomenon. Optical
Proximity Correction (OPC) has been used for overcoming oval hole shape. Through the result of OPC modeling and
simulation, we could get optimized mask bias of hole. Sometimes, good experimental data will be help for this modeling
and OPC process. From these OPC simulation and experimental data, most compatible rule based OPC process could be
developed. In this paper, we suggest the method of improving oval hole shape by using OPC simulation and making rule
base OPC process from experimental data.
For the 90nm node and beyond, smaller Critical Dimension(CD) control budget is required and the ways to control good
CD uniformity are needed. Moreover Optical Proximity Correction(OPC) for the sub-90nm node demands more accurate
wafer CD data in order to improve accuracy of OPC model. Scanning Electron Microscope (SEM) is the typical method
for measuring CD until ArF process. However SEM can give serious attack such as shrinkage of Photo Resist(PR) by
burning of weak chemical structure of ArF PR due to high energy electron beam. In fact about 5nm CD narrowing occur
when we measure CD by using CD-SEM in ArF photo process. Optical CD Metrology(OCD) and Atomic Force
Microscopy(AFM) has been considered to the method for measuring CD without attack of organic materials. Also the
OCD and AFM measurement system have the merits of speed, easiness and accurate data. For model-based OPC, the
model is generated using CD data of test patterns transferred onto the wafer. In this study we discuss to generate accurate
OPC model using OCD and AFM measurement system.
In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most
important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification.
They have continuously developed and introduced new methods to achieve more accurate results of OPC verification.
The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification
process, because more time and human resource are needed to inspect the result of verification as increasing false errors.
A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they
are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or
filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false
error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for
filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of
area size with different corner length, we could get more accurate and efficient results and decrease the time for review
to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using
different size of CD error non-checking area with various corner lengths is presented.
Conventional OPC fragmentation method operates under a set of simple guiding principles. All patterns are to be
uniform in finite size from edge of polygon. Within each fragment, the intensity profile (aerial image) and edge-placement
error (EPE) are calculated at a settled location. Finally, the length of the entire fragment is moved to correct
for the EPE at that location. This is to be often against simulation like a model based OPC. In the strict sense, model
based OPC is depended on simulation results not only moving of all fragments in the layout are reduced to zero but also
dividing of all polygon edges. This drastically increased data volume and the computation time required to perform OPC.
Therefore, more powerful fragmentation mechanism will be one of major factors for the success of OPC process.
In this study, a new approach of fragmentation has been tested, which reduces OPC correction error. First, we check
the weak point of all patterns using slope, EPE, MEEF and contrast. Second, weak points apply high frequency
fragmentation based on simulation contour images. The others are divided into normal correction recipe. This improves
to accurate OPC correction for weak point which can divide a fine classification. It also is possible to reduce OPC time
for non critical pattern applied moderate fragmentation.