As semiconductor product development based on shrinkage continues, the accuracy and difficulty required for the model based optical proximity correction (MBOPC) is increasing. OPC simulation time, which is the most timeconsuming part of MBOPC, is rapidly increasing due to high pattern density in a layout and complex OPC model.
To reduce OPC simulation time, we attempt to apply graphic processing unit (GPU) to MBOPC because OPC process is good to be programmed in parallel. We address some issues that may typically happen during GPU-based OPC simulation in multi thread system, such as “out of memory” and “GPU idle time”. To overcome these problems, we propose a thread scheduling method, which manages OPC jobs in multiple threads in such a way that simulations jobs from multiple threads are alternatively executed on GPU while correction jobs are executed at the same time in each CPU cores. It was observed that the amount of GPU peak memory usage decreases by up to 35%, and MBOPC runtime also decreases by 4%. In cases where out of memory issues occur in a multi-threaded environment, the thread scheduler was used to improve MBOPC runtime up to 23%.
Advances on techniques that enable small technology nodes printing benefit the lithography with cost. For instance, lens heating draws people's attention when the NTD process is applied together with the bright tone mask. And the study of it requires the investigation of many other variables. In this paper we examine individual impact of several closely related process variables to understand the lens heating behavior. Meanwhile, though it is known that the PTD process is less sensitive to the lens heating effect, we do observe mask topography induced best focus shifts among different patterns with small spaces. It is of interest to discover the extent to which the NTD is affected. Thus in this paper we also compared the two processes with respect to the mask topography effect by simulating the best focus shifts of a series of test patterens.
This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node
DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation)
control become more important to meet the performance goal for high speed in DRAM. The main factors which
influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is
required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied
new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of
interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density
difference between spider mask and real gate mask, the skew difference occurs between them. We tested the
effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10
mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the
ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm).
This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in
real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch
skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce
this skew difference between spider mask and real mask, we applied open field mask correction term and long
range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy
of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
Optical proximity correction (OPC) of contact-hole printing is challenging since its two dimensional shapes requires
through understanding of lithographic processes compared to one dimensional line and space pattering. Moreover,
recently, it is common to use "elongated contact holes" with large contact area, rather than simple circular ones, for small
electrical resistance. These elongated contact holes make it even more difficult to generate a good OPC model than the
circular ones because the elongated contact-hole patterning causes the asymmetric process effects. For example, impacts
of mask CD error, resist diffusion and resist development are different depending on the orientation of the elongated
contact holes. This paper presents how the OPC model for the elongated contact-hole can be improved as the mask CD
error compensation, accurate resist diffusion model and a new Variable Threshold Model (VTM) are applied for the
asymmetric process effects.
It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard
OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely
long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light
implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and
presents how to solve the problems.
Traditional approach to model based optical proximity correction method is to collect a set of 1-D and
2-D test pattern data, calibrate a scalar or vector model at constant or variable threshold and modify the
physical layout to obtain the desired layout. Optical proximity corrected layout is obtained by minimizing
the error between the target and the printed image iteratively using a calibrated single model to generate a
simulated print image of mask pattern of variety of field polarity. A similar approach can be extended to
incorporate the final silicon image using a lumped model or tandem photo-resist development and etch
process models. Recently, some have begun to incorporate differing models at specific regions of the
The basic underlying assumption of a model-based OPC requires one to generate a simulated contour
that provides close approximation of wafer image using a calibrated model. During iterative OPC
procedure, not all of the regions of OPC polygons are simulated. That is, sparse sampling of each polygon
is performed to reduce the number of error calculations required and such calculation points are referred to
as an evaluation site. A careful selection of sampling site must be performed to capture optical proximity
effect and obtain the desired OPC. In this paper, utilization of multiples models to generate contour to
accurately define the 2D pattern locally, and implementation of its models throughout the layout is
presented in order to improve accuracy of variety of contact pattern types present in a layout. Hence, the
basic concept is to apply differing models at localized region and achieve greater OPC accuracy than a
single calibrated model.
In particular, a target layout may contain a contact and bar-type structures for the purpose of device
fabrication process step simplifications. Essentially, two different pattern types need to be OPCed, and in
order to perform model based OPC on such a layout, a model for each contact type is generated separately
using a best-fit adaptive search method of optical illumination conditions, aerial image diffusion parameter
and double Gaussian mask loading terms as a main regression parameters. As it terms out, it is difficult to
generate a single model that calibrates to both the contact and bar-type structures and a distinct shift in
empirically calibrated threshold levels exists, and a preferred method is to generate models suited for
contact and bar-type structures separately in order to improve the model and OPC accuracy. However,
each model type needs to be applied at specific locations of a pattern, and a proper OPC recipe for handling
biasing of each pattern type is needed as well as correction scheme suitable for each pattern type is required.
In this paper, we describe an OPC methodology for merged direct contact layout using a proposed pattern
specific modeling and correction technique, and the experimental results indicate that this methodology provides ADI 3s target skew value of 14 nm and ACI 3σ target skew value of 17 nm on a 60 nm half pitch
Virtual OPC concept is suggested for soothing the problem that the roadmap of semiconductor devices proceeds the rate of development of exposure tools. Virtual OPC uses the simulated CD data for an OPC modeling instead of the measured CD data. For successful virtual OPC, the extreme accuracy of the simulation is required for obtaining the simulated CD data close to the actual CD values. In this paper, our efforts to enhance the simulation accuracy are presented and the accuracy of simulated sample data for OPC is verified. The applicability of virtual OPC to the production of devices was verified by performing the virtual OPC using the simulated sample data at 1.2 NA lithography and the result also is presented.
ArF is still being used as a main light source for lithography of critical layers due to development delay of alternative
light sources. The resolution enhancement is therefore mainly depends on increasing the NA of the projection lens or on
decreasing the k1 value. Depth-of-focus is becoming narrower in both the approaches than ever. It has been well-known
that properly designed assist-features can improve the process window of lithography, but optimizing assist-features is
generally not a simple task, unless the pattern area is small or all the patterns are well isolated so that the proximity
effect can be safely ignored. It is challenging to generate assist-features automatically when the pattern area is not small
or the patterns are not well isolated, both of which is not a case in today's memory devices. Today's memory chip has
such a large pattern area that it easily occupies a large portion of the available imaging field of today's scanner. The
proximity effect cannot be safely ignored because k1 factor is low in today's memory devices and the patterns are not
isolated even in peripherals. A new method to generate assist-features has been internally developed. This method is
based on optical simulation and utilizes the optical characteristic of the exposure tool to maximize the process margin,
and is scalable to the full-chip scale. Side-lobes are automatically suppressed well under the imaging threshold. The
total processing time is comparable to a usual model OPC processing time. The present paper demonstrates a test case
of this new method to a contact layer of full-chip sub-70nm DRAM device and the improvement of depth-of-focus. The
increased depth-of-focus was equivalent to 18% reduction of contact CD at the same depth-of-focus.
Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask
topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model
error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such
as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is
also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a
good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the
phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.
In order to perform an optical proximity correction of memory device nodes below half-pitch 50nm, so called 3D mask
effects need to be included in a model based OPC. As the mask pitch approaches wavelength of an optical system, and
the angle of off-axis illumination becomes increasingly greater than normal incident beam, combined effects of
transmission loss and mask induced polarization induces deviations from Kirchhoff thin mask approximation. Presently,
just a handful of methods are being developed for commercial use in full-chip scale optical proximity correction: edge
domain decomposition method (DDM), rim-type boundary layer and more recently, M3D model [1-6]. However, these
methods currently require extensive modeling and proximity correction runtime although its methods are being
continously improved for accuracy and speed. In this work, some results on an alternative approach to 3D mask
modeling that is suitable for OPC are presented. Using modeling test pattern experimental data and FDTD rigorous
simulation results, a thin mask approximation and alternative 3D mask approximate approaches are compared. And the
results indicate improved model accuracy in terms of root mean square of 30% for a cross-pole and a dipole illumination
conditions, respectively, while the OPC run-time remained similar. Furthermore, a flash memory gate-poly OPC results
using the 3D mask approximate model indicates improved correlation to experimental results than a thin mask model at
minimum resolution dense feature and narrow space regions.
Thin mask and proposed approximate 3D mask models were calibrated for three differing illumination conditions: two
X-dipole illuminations with Y-linear polarization and cross-pole quasar illumination with X&Y-linear polarization
states. For each of the extreme off-axis illumination conditions, 3D mask approximate model developed for OPC
indicated improved calibration results to both test pattern wafer images and rigorous simulation results. In addition,
OPC layout image contours of 3D mask approximate model correlated better to wafer image than the thin mask
approximation at nominal and defocus conditions.
We present simplified symmetric boundary layer model (BLM) for Optical Proximity Correction (OPC) in order to account for thick (or 3D or topographic) mask effect. In this approach, near-field mask image which is quite different from original mask pattern due to mask topography is approximated as the original pattern and boundary layer around it. In this work, the boundary layer is determined as such that residual critical dimension (CD) error between measured CD and modeled CD from the BLM is minimized for various types of features. In case of sub-50 nm memory patterning, this BLM shows sufficient accuracy that root mean square of the residual CD is as small as 4.3 nm. Also, OPC speed with BLM is reasonably fast as the OPC time with BLM increases as only around twice as the conventional OPC time without BLM, which is acceptable in practice.
Most of simulation tools and OPC engines use Kirchhoff (thin mask) approximation for imaging calculation. Some commercial simulation tools have implemented the rigorous algorithm to solve the Maxwell's equations for the electric and magnetic fields. Currently, a rigorous algorithm is being used for the case of high topographical mask such as CPL and alternating PSM. However, the mask topographical effect of binary mask and attenuated PSM is not negligible in the case of hyper NA lithography. Implementing the rigorous algorithm on full chip OPC is impractical due to its OPC runtime limitation. Thin mask and rigorous simulation modeling are compared to check whether the current algorithms of OPC tools can sufficiently reflect the mask topography effect of hyper NA lithography and whether a combination of currently usable algorithms can cover the mask topography effect. OPC modeling is generally executed based on measured CD data. However we do not have usable hyper NA scanners, so the OPC modeling is executed based on full physical simulation data to the resist image, which we will define as a "Virtual OPC modeling".
Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.
Dummy contact generation procedure to apply off-axis illumination (OAI) to a contact layer in a 60 nm node device is described. The model based optical proximity correction (OPC) is also adopted to control the on-chip variation (OCV). The dummy contact size of 110 nm with the space distance of 90 nm between the main and dummy contact is used. By applying OPCed contact, the proximity variation is reduced less than 11 nm from 49 nm. The modeling methods are assessed by comparing delta edge placement error (EPE) values, which represent the model accuracy. The VTR_E model is shown to well correct the proximity variation, and it is adopted in our experiment.
Applying to the arbitrary patterns of logic device and to generate more dummy patterns, the rule needs to be modified. The modified rule includes the dummy merge method, and the dummy contacts are automatically generated for the contact layer of 60 nm node logic device.