Transferring the image information in analog form between the FPA and the external electronics causes the disturbance of the outside noise. On-chip A/D converter into the readout circuit (ROIC) can eliminate the possibilities of the cross-talk of noise. Also, the information can be transported more efficiently in power in the digital domain compared to the analog domain. In designing on-chip A/D converter for cooled type high density infrared detector array, the most stringent requirements are power dissipation, number of bits, die area and throughput. In this study, pipelined type A/D converter was adopted because it has high operation speed characteristics with medium power consumption. Capacitor averaging technique and digital error correction for high resolution was used to eliminate the error which is brought out from the device mismatch. The readout circuit was fabricated using 0.6μm CMOS process for 128 x 128 mid-wavelength infrared (MWIR) HgCdTe detector array. Fabricated circuit used direct injection type for input stage, and then S/N ratio could be maximized with increasing the integration capacitor. The measured performance of the 14 b A/D converter exhibited 0.2 LSB differential non-linearity (DNL) and 4LSB integral non-linearity (INL). A/D converter had a 1 MHz operation speed with 100mW power dissipation at 5V. It took the die area of 5.6 mm2. It showed the good performance that can apply for cooled type high density infrared detector array.
In this paper, a readout technique involving current mode background suppression is studied for 2-dimensional infrared focal plane arrays (IR FPA’s). This technique has a current memory per pixel, and the suppression current can be optimized per pixel element. Capacitive transimpedende amplifier (CTIA) and feedback amplifier structure are adopted for input circuit and background suppression circuit, respectively. Feedback amplifier structure can minimize skimming error due to channel length modulation. The area size of the pixel circuit is generally limited in the case of 2-D application. So, the amplifier used in the CTIA input circuit adopts timesharing for background suppression. To further improve the area limitation, a half circuit of the CTIA is shared in row circuit out of the pixel array. Because of the leakage of the current memory, the skimming data of the current memory in the pixel array is stored in SRAM array through ADC, and is refreshed periodically with SRAM data through DAC.
The readout circuit was fabricated using 0.6um 2-poly 3-metal CMOS process for 64 x 64 LWIR HgCdTe IR array with the pixel size of 50um x 50um. The measurement performance of the skimming circuit exhibits about only 3% error for 100nA background current. The simulation results exhibit that skimming error can be reduced further to 0.3% when the ratioed current mirror scheme and/or multi step refresh scheme is adopted.
Noise property is a prime consideration in designing readout circuits for IR focal plane arrays. Output stage is frequently a dominant noise source in the readout circuit. From this pont of view, we suggest a new noise reduction circuit, which suppresses the noise bandwidth of the output stage. The Noise Bandwidth Suppression (NBS) circuit, which is a RC filter with bistable bandwidth, reduces dynamically the niose bandwidth with the same operation speed. From experimental results, it is found that the NBS circuit can successfully reduce the read noise. Using NBS and CDS, the output stage noise was down to 168μVrms at 300K. It is expected that the output stage noise will be reduced to about μVrms at the operation temperature of 77K and the designed readout circuit can satisfy 95% BLIP condition.