As industry prepares to introduce extreme ultraviolet (EUV) technology for the coming sub-10-nm lithography, this paper presents metrology approaches that utilize the prevalent Critical Dimension Scanning Electron Microscope (CD-SEM). Two technical approaches will be discussed. One is comprehensive solutions for new EUV characterized features, such as low resist-shrinkage electron beam optics and high efficiency metrology/inspection for EUV process monitoring. The other, like conventional minimization processes, is down-to-ångström-order metrology methodologies required for stricter CD process control. This paper is the first to conceptualize specifications for a stringent and multi-index tool matching, namely “atomic matching,” which is considered as a crucially important feature of any in-line metrology tools in the EUV era.
Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, power spectrum densities (PSD) prediction, sampling strategy, and noise mitigation. General guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as the wave-matching method are shown to be effective for robustly detecting edges from low SNR images, whereas a conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. An advanced PSD prediction method such as the multitaper method is effective in suppressing sampling noise within a line edge to analyze, whereas a number of lines are still required for suppressing line-to-line variation. Two types of SEM noise mitigation methods, such as the “apparent noise floor” subtraction method and LER-noise decomposition using regression analysis, are verified to successfully mitigate SEM noise from PSD curves. These results are extended to local critical-dimension uniformity (LCDU) measurement to clarify the impact of SEM noise and sampling noise on LCDU.
Proc. SPIE. 10585, Metrology, Inspection, and Process Control for Microlithography XXXII
KEYWORDS: Line edge roughness, Scanning electron microscopy, Edge detection, Signal to noise ratio, Critical dimension metrology, Detection and tracking algorithms, Metrology, Reliability, Process control, Image filtering
Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, PSD prediction, sampling strategy, and noise mitigation, and general guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as wave-matching method are shown effective for robustly detecting edges from low SNR images, while conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. Advanced PSD prediction method such as multi-taper method is effective in suppressing sampling noise within a line edge to analyze, while number of lines is still required for suppressing line to line variation. Two types of SEM noise mitigation methods, "apparent noise floor" subtraction method and LER-noise decomposition using regression analysis are verified to successfully mitigate SEM noise from PSD curves. These results are extended to LCDU measurement to clarify the impact of SEM noise and sampling noise on LCDU.
Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. Especially, DSA lithography using coordinated line epitaxy (COOL) process is obviously one of candidates which could be the first generation of DSA applying PS-b-PMMA block copolymer (BCP) for sub-15nm dense line patterning . DSA can enhance the pitch resolutions, and can mitigate CD errors to the values much smaller than those of the originally exposed guiding patterns. On the other hand, local line placement error often results in a worse value, with distinctive trends depending on the process conditions. To address this issue, we introduce an enhanced measurement technology of DSA line patterns with distinguishing their locations in order to evaluate nature of edge placement and roughness corresponding to individual pattern locations by using images of CD-SEM. Additionally correlations among edge roughness of each line and each space are evaluated and discussed. This method can visualize features of complicated roughness easily to control COOL process. As a result, we found the followings. (1) Line placement error and line placement roughness of DSA were slightly different each other depending on their relative position to the chemical guide patterns. (2) In middle frequency area of PSD (Power Spectral Density) analysis graphs, it was observed that shapes were sensitively changed by process conditions of chemical stripe guide size and anneals temperature. (3) Correlation coefficient analysis using PSD was able to clarify characteristics of latent defect corresponding to physical and chemical property of BCP materials.
Grapho-epitaxy based hole shrink process of Directed Self-assembly (DSA) is one of the candidates for less than 30 nm hole pattern fabrication. The guide patterns of grapho-epitaxy are made by using ArF immersion scanner under the condition of near resolution limit to the 193-nm exposure. Hence, guide patterns have measurable level of edge roughness and edge placement errors. Those errors cause serious size errors and placement errors of DSA hole patterns. RED (Robust Edge Detection) is a new measurement function of CD-SEM for qualifying guide pattern shapes and DSA pattern shapes simultaneously. We also propose GBM (Grid Based Metrology) for the measurement of DSA hole's absolute placement error. In this paper, we applied the two methods for qualifying about 20 nm-node’s different polymer film thickness of DSA hole process. The DSA placement error from GBM result and relative DSA placement error obtained by RED are almost same as about 3nm (3sigma). This indicates both RED and GBM methods are correct to measure the DSA process error.
Scanning electron-microscope (SEM) has been successfully applied to CD measurement as promising tools for qualifying and controlling quality of semiconductor devices in in-line manufacturing process since 1985. Furthermore SEM is proposed to be applied to in-die overlay monitor in the local area which is too small to be measured by optical overlay measurement tools any more, when the overlay control limit is going to be stringent and have un-ignorable dependence on device pattern layout, in-die location, and singular locations in wafer edge, etc. In this paper, we proposed new overlay measurement and inspection system to make an effective use of in-line SEM image, in consideration of trade-off between measurement uncertainty and measurement pattern density in each SEM conditions. In parallel, we make it clear that the best hybrid overlay metrology is in considering each tool’s technology portfolio.
Besides feature size control of advanced semiconductor device manufacturing, critical dimension (CD) measurement SEMs are also indispensable tools for the development of advanced semiconductor manufacturing equipment or new semiconductor manufacturing materials. Especially in the case of advanced stepper and resist development for ultra micro patterns where the role of CD-SEMs is particularly important for evaluation specific samples, such as focus exposure matrix (FEM). An FEM sample is a wafer that has hundreds to thousands of patterns created with varying resist exposure dosage and Stepper focuses. As a result, the pattern shape and the line width vary dramatically within one wafer and the number of CD-SEM measurement points necessary to evaluate such FEM samples also increases drastically with decreasing semiconductor design rules. Thus, a CD-SEM that can measure FEM samples with high throughput and high reliability is strongly desired. For this purpose Hitachi has developed a new pattern detection algorithm. This algorithm detects a target and judges the quality of the actual pattern by using criteria similar to those a human operator might use when measuring the sample. With this method implemented on a Hitachi CD-SEM S-9200 we achieved a highly automated, fast and accurate measurement of FEM samples on which conventional algorithms failed.
New packaging techniques for opto-electronic multichip modules (OE-MCMs), including OE substrates and optical coupling between a waveguide and a flip-chip bonded photodevice or fiber, are presented for high-speed and wide-band communication systems. The OE substrates, which offer high-density, high-speed optical and electrical interconnection, are made from low loss (0.4 dB/cm) optical polyimide waveguides fabricated on copper-polyimide electrical multilayer substrates. A total internal reflection mirror fabricated at the edge of the optical waveguide reflects the light propagating from the waveguide to a flip-chip bonded photodiode with a loss of less than 1.5 dB. The waveguides are coupled to fibers for inter-module interconnection using the self-aligning fiber guiding method.